公开(公告)号：US20230147848A1

公开(公告)日：2023-05-11

申请号：US18151089

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Tsu-Hui Su ,  Ssu-Yu Liao ,  Chun-Hsiang Fan ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L21/30604 ,  H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L22/12

Abstract: A method includes depositing a silicon layer over a semiconductor region, forming dielectric isolation regions extending into the silicon layer and the semiconductor region, and recessing the dielectric isolation regions. A first portion of the silicon layer and a second portion of the semiconductor region are between the dielectric isolation regions, and protrude higher than top surfaces of the dielectric isolation regions to form a semiconductor fin. The semiconductor fin is thinned, and after the first semiconductor fin is thinned, the first portion of the silicon layer remains. A gate stack is formed on the semiconductor fin.

公开(公告)号：US20220367254A1

公开(公告)日：2022-11-17

申请号：US17871042

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20220172945A1

公开(公告)日：2022-06-02

申请号：US17670990

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Hong-Jie Yang ,  Chia-Ying Lee ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/027 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

公开(公告)号：US20210391449A1

公开(公告)日：2021-12-16

申请号：US16899119

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Yu Liao ,  Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/161 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8238

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

公开(公告)号：US11133200B2

公开(公告)日：2021-09-28

申请号：US15797676

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Liang Tai ,  Chun-Hsiang Fan ,  Kuo-Bin Huang ,  Ming-Hsi Yeh

IPC: H01L21/67 ,  B05D1/00 ,  B05D3/00 ,  B08B3/10 ,  H01L21/02 ,  H01L21/687 ,  B05B3/02

Abstract: A method of processing a semiconductor substrate is provided. The semiconductor substrate may be placed on a spin chuck with a plurality of holding members, each holding member including a pin having a sloped portion to provide a gap between an upper edge of the substrate and the pin. Thereafter, one or more treatment fluids may be dispensed over the substrate.

公开(公告)号：US10699944B2

公开(公告)日：2020-06-30

申请号：US16145457

申请日：2018-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/48 ,  H01L21/306

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US10170317B1

公开(公告)日：2019-01-01

申请号：US15718565

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/66

Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

公开(公告)号：US20250056823A1

公开(公告)日：2025-02-13

申请号：US18931886

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US12136566B2

公开(公告)日：2024-11-05

申请号：US17969396

申请日：2022-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US20240282575A1

公开(公告)日：2024-08-22

申请号：US18638436

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo-Bin Huang

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/095 ,  G03F7/20 ,  G03F7/32 ,  H01L21/02 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/0273 ,  G03F7/094 ,  G03F7/20 ,  G03F7/32 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  G03F7/095 ,  H01L21/30608

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.