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    APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY
    31.
    发明申请
    APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY 有权
    存储器中缓存写入命令的设备和方法

    公开(公告)号：US20100250874A1

    公开(公告)日：2010-09-30

    申请号：US12410288

    申请日：2009-03-24

    申请人： Todd D. Farrell ,  Jeffrey P. Wright ,  Victor Wong ,  Alan J. Wilson

    发明人： Todd D. Farrell ,  Jeffrey P. Wright ,  Victor Wong ,  Alan J. Wilson

    IPC分类号： G06F12/00

    CPC分类号： G11C7/22 ,  G06F13/161 ,  G11C2207/2218

    摘要： Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command.

    摘要翻译： 存储器，缓冲写入命令电路和用于在存储器中执行存储器命令的方法。 在一些实施例中，在写入命令之后接收的读取命令在执行先前接收的写入命令之前在内部执行。 写入命令被缓冲，以便在完成稍后接收的读取命令时可以执行命令。 缓冲写入命令电路的一个示例包括写入命令缓冲器以缓冲写入命令并且响应于时钟信号传播缓冲的写入命令，并且还包括写入命令缓冲器逻辑。 写命令缓冲器逻辑产生一个活动时钟信号，通过写命令缓冲区来传送缓冲的写入命令，以便执行，响应在接收到写入命令之后接收到一个读取命令，暂停有效的时钟信号，并在完成后重新启动激活的时钟 的后来收到的read命令。

    Electronic musical performance instrument with greater and deeper creative flexibility
    33.
    发明授权
    Electronic musical performance instrument with greater and deeper creative flexibility 失效
    电子音乐表演乐器具有更大更深的创意灵活性

    公开(公告)号：US07692090B2

    公开(公告)日：2010-04-06

    申请号：US10758177

    申请日：2004-01-15

    申请人： Craig Negoescu ,  Lary Cotton ,  Victor Wong

    发明人： Craig Negoescu ,  Lary Cotton ,  Victor Wong

    IPC分类号： B27B29/08

    CPC分类号： G10H7/006 ,  G10H2240/285

    摘要： An electronic musical performance instrument that provides a user with a wide array of creative choices of operating systems, sound synthesis applications, user interfaces (including those emulating the interface of a conventional musical instrument and electronic control interfaces), supporting infrastructure components such as MIDI cards, sound cards, storage devices thus providing the performance artist with greater and deeper creative flexibility.

    摘要翻译： 一种电子乐器，为用户提供操作系统，声音合成应用程序，用户界面（包括仿真传统乐器和电子控制接口的接口的用户界面）的各种创意选择，支持基础设施组件，如MIDI卡 ，声卡，存储设备，从而为表演艺术家提供更大更深的创意灵活性。

    Conversational advertising
    35.
    发明申请
    Conversational advertising 审中-公开
    对话广告

    公开(公告)号：US20090094517A1

    公开(公告)日：2009-04-09

    申请号：US11986914

    申请日：2007-11-27

    申请人： Jonathan S. Brody ,  Victor Wong

    发明人： Jonathan S. Brody ,  Victor Wong

    IPC分类号： G06F3/048

    CPC分类号： G06Q30/02

    摘要： A method of advertising in a computer medium, such as the Internet. The method includes providing a virtual instructor in a virtual environment. The virtual instructor is configured to provide content, such as, a foreign language instruction or a translation service of existing foreign language web pages to a user over the Internet. In the substantive content, the virtual instructor embeds or hides promotional content in the substantive content. This promotional content can be a spoken advertisement to the user. The promotional content can be introduced in a subtle manner, and does not distract the user from the lesson. The advertisement may be spoken to the user by the virtual instructor at the time the educational content is provided to the user.

    摘要翻译： 一种在诸如因特网的计算机介质中进行广告的方法。 该方法包括在虚拟环境中提供虚拟教练。 虚拟教练被配置为通过因特网向用户提供诸如外语指令或现有外语网页的翻译服务的内容。 在实质内容中，虚拟教练将宣传内容嵌入或隐藏在实质内容中。 该促销内容可以是对用户的口头广告。 促销内容可以以微妙的方式引入，不会使用户注意力不集中。 在将教育内容提供给用户时，可以由虚拟教练向用户说出该广告。

    INDIVIDUAL I/O MODULATION IN MEMORY DEVICES
    36.
    发明申请
    INDIVIDUAL I/O MODULATION IN MEMORY DEVICES 有权
    内存设备中的个性I / O调制

    公开(公告)号：US20080219067A1

    公开(公告)日：2008-09-11

    申请号：US12124942

    申请日：2008-05-21

    申请人： Mehul Nagrani ,  Victor Wong ,  Jeffrey P. Wright

    发明人： Mehul Nagrani ,  Victor Wong ,  Jeffrey P. Wright

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08

    摘要： A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

    摘要翻译： 一种具有降低功耗的DRAM电路，在某些情况下，存储器阵列存取速度更快。 与阈值电容/长度相比，根据其电容/长度来感测连接到存储器阵列的输入/输出线。 比阈值更短或更低电容性的输入/输出线比比阈值更长，更容性的输入/输出线被感测得更早。 由于更短的输入/输出线路被更快地感测到，所以它们需要更少的功率并且可以更快地访问。

    Individual I/O modulation in memory devices
    37.
    发明授权
    Individual I/O modulation in memory devices 有权
    存储设备中的单独I / O调制

    公开(公告)号：US07388794B2

    公开(公告)日：2008-06-17

    申请号：US11447272

    申请日：2006-06-06

    申请人： Mehul Nagrani ,  Victor Wong ,  Jeffrey P. Wright

    发明人： Mehul Nagrani ,  Victor Wong ,  Jeffrey P. Wright

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08

    摘要： A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

    摘要翻译： 一种具有降低功耗的DRAM电路，在某些情况下，存储器阵列存取速度更快。 与阈值电容/长度相比，根据其电容/长度来感测连接到存储器阵列的输入/输出线。 比阈值更短或更低电容性的输入/输出线比比阈值更长，更容性的输入/输出线被感测得更早。 由于更短的输入/输出线路被更快地感测到，所以它们需要更少的功率并且可以更快地访问。

    Individual I/O modulation in memory devices
    38.
    发明申请
    Individual I/O modulation in memory devices 有权
    存储设备中的单独I / O调制

    公开(公告)号：US20060221671A1

    公开(公告)日：2006-10-05

    申请号：US11447272

    申请日：2006-06-06

    申请人： Mehul Nagrani ,  Victor Wong ,  Jeffrey Wright

    发明人： Mehul Nagrani ,  Victor Wong ,  Jeffrey Wright

    IPC分类号： G11C11/24

    CPC分类号： G11C7/08

    摘要： A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The out/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

    摘要翻译： 一种具有降低功耗的DRAM电路，在某些情况下，存储器阵列存取速度更快。 与阈值电容/长度相比，根据其电容/长度来感测连接到存储器阵列的输入/输出线。 比阈值更短或更低电容性的输出/输出线比比阈值更长，更容性的输入/输出线被检测得更早。 由于更短的输入/输出线路被更快地感测到，所以它们需要更少的功率并且可以更快地访问。