公开(公告)号：US20230087151A1

公开(公告)日：2023-03-23

申请号：US17502692

申请日：2021-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Grebs ,  Meng-Chia Lee ,  Hong Yang ,  Ya ping Chen ,  Sunglyong Kim

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A trench gate metal oxide semiconductor (MOSFET) device includes a substrate with a semiconductor surface layer doped a first conductivity type. At least one trench gate MOSFET cell is located in or over the semiconductor surface layer, and includes a body region in the semiconductor surface layer doped a second conductivity type, and a source region on top of the body region doped the first conductivity type. A trench extends down from a top side of the semiconductor surface layer, the trench abutting the body region and being lined with a dielectric material. A field plate that includes polysilicon is located in the trench, and a gate electrode is located over the field plate. The field plate has a bottom portion, a middle portion, and a top portion, wherein the bottom portion is narrower than the middle portion, and the middle portion is narrower than the top portion.

公开(公告)号：US11532560B2

公开(公告)日：2022-12-20

申请号：US14531177

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Yufei Xiong ,  Hong Yang

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L21/311

Abstract: In a semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

公开(公告)号：US20220093754A1

公开(公告)日：2022-03-24

申请号：US17167911

申请日：2021-02-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Peng Li ,  Ya ping Chen ,  Yunlong Liu ,  Hong Yang ,  Shengpin Yang ,  Jing Hu ,  Chao Zhuang

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

公开(公告)号：US09825138B2

公开(公告)日：2017-11-21

申请号：US15188188

申请日：2016-06-21

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Zachary K. Lee ,  Yufei Xiong ,  Yunlong Liu ,  Wei Tang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/407 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7834

Abstract: A method of fabricating a FET includes forming a gate on the surface of a substrate. A trench contact extends between a first region located proximate the surface of the substrate and a second region located below the first region is formed in the surface. The surface of the substrate is coated with a conductive material, wherein the conductive material at least partially covers the gate and lines the trench contact to electrically connect the first region and the second region. A void remains in the trench contact. A dielectric material is applied to the conductive material, wherein the dielectric material at least partially fills the void in the trench contact. At least a portion of the conductive material is etched from the gate.

公开(公告)号：US20170288052A1

公开(公告)日：2017-10-05

申请号：US15622869

申请日：2017-06-14

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

公开(公告)号：US09711639B2

公开(公告)日：2017-07-18

申请号：US15049209

申请日：2016-02-22

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hong Yang

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/28114 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66734

Abstract: A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches.

公开(公告)号：US09397180B1

公开(公告)日：2016-07-19

申请号：US14695290

申请日：2015-04-24

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Seetharaman Sridhar ,  Yufei Xiong ,  Yunlong Liu ,  Zachary K. Lee ,  Peng Hu

IPC: H01L21/00 ,  H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L21/3215 ,  H01L21/265

CPC classification number: H01L29/41766 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/743 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835

Abstract: An semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material. A method for forming a semiconductor device with a low resistance sinker contact wherein the low resistance sinker contact is etched through a first doped layer and is etched into a second doped layer and wherein the first doped layer overlies the second doped layer and wherein the second doped layer is more heavily doped that the first doped layer and wherein the low resistance sinker contact is filled with a metallic material.

Abstract translation: 一种具有低电阻沉降接触的半导体器件，其中低电阻沉降片接触被蚀刻穿过第一掺杂层并被蚀刻到第二掺杂层中，并且其中第一掺杂层覆盖在第二掺杂层上，并且其中第二掺杂层更重 掺杂了第一掺杂层，并且其中低电阻沉降片接触体填充有金属材料。 一种用于形成具有低电阻沉降接触的半导体器件的方法，其中所述低电阻沉降片接触被蚀刻通过第一掺杂层并且被蚀刻到第二掺杂层中，并且其中所述第一掺杂层覆盖所述第二掺杂层，并且其中所述第二掺杂 所述第一掺杂层更加重掺杂，并且其中所述低电阻沉降片接触体填充有金属材料。

公开(公告)号：US20160126193A1

公开(公告)日：2016-05-05

申请号：US14531177

申请日：2014-11-03

Applicant: Texas Instruments Incorporated

Inventor： Yunlong Liu ,  Yufei Xiong ,  Hong Yang

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/02 ,  H01L21/321 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53295 ,  H01L21/31111 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an semiconductor process, a seamless tungsten plug is formed in an inter-layer dielectric by forming the inter-layer dielectric from multiple oxide layers having different wet etch rates, from lowest wet-etch rate for the lowest layer to highest wet-etch rate for the highest layer, forming a hole or trench in the inter-layer dielectric using a dry etch process, reconfiguring the hole or trench to have sloped side walls by performing a wet etch step, and filling the hole or trench with tungsten and etching back the tungsten to form a seamless tungsten plug.

Abstract translation: 在半导体工艺中，通过从具有不同湿蚀刻速率的多个氧化物层形成层间电介质，从最低层的最低湿蚀刻速率到最高湿蚀刻速率，在层间电介质中形成无缝钨插塞 对于最高层，使用干蚀刻工艺在层间电介质中形成孔或沟槽，通过执行湿蚀刻步骤来重新配置孔或沟槽以具有倾斜的侧壁，并用钨填充孔或沟槽并蚀刻回 钨形成无缝钨丝塞。

公开(公告)号：US09230851B2

公开(公告)日：2016-01-05

申请号：US14175488

申请日：2014-02-07

Applicant: Texas Instruments Incorporated

Inventor： Simon John Molloy ,  Christopher Boguslaw Kocon ,  John Manning Savidge Neilson ,  Hong Yang ,  Seetharaman Sridhar ,  Hideaki Kawahara

IPC: H01L21/336 ,  H01L21/763 ,  H01L29/66

CPC classification number: H01L21/763 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7811

Abstract: A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer.

Abstract translation: 制造半导体器件的方法包括从半导体层的顶侧形成至少一个沟槽，其中沟槽衬有沟槽电介质衬垫并由第一多晶硅层填充。 蚀刻沟槽电介质衬垫的表面，其中沟槽电介质衬里中的凹陷相对于第一多晶硅层的顶表面形成，导致形成包括第一多晶硅层的突起。 蚀刻第一多晶硅层以去除突起的至少一部分。 在蚀刻第一多晶硅层之后，至少在沟槽上形成第二电介质层。 沉积第二多晶硅层。 蚀刻第二多晶硅层以将其去除在沟槽上并且在半导体层的顶侧上提供图案化的第二多晶硅层。