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58 条记录 (耗时 0.019 秒)

    Method for producing and/or renewing an etching mask
    33.
    发明授权
    Method for producing and/or renewing an etching mask 失效
    用于制造和/或更新蚀刻掩模的方法

    公开(公告)号：US06806037B2

    公开(公告)日：2004-10-19

    申请号：US10167785

    申请日：2002-06-12

    申请人： Matthias Goldbach ,  Thomas Hecht ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Thomas Hecht ,  Bernhard Sell

    IPC分类号： G03F726

    CPC分类号： H01L21/3086 ,  H01L21/3081 ,  H01L21/3085

    摘要： An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

    摘要翻译： 制造用于通过曝光的光致抗蚀剂层蚀刻基板的蚀刻掩模，使得暴露一次的区域尚未完全曝光，并且基于位于光致抗蚀剂层下方的反射层，额外暴露的区域完全暴露 。 因此，用于蚀刻衬底的第一蚀刻掩模可以通过第二蚀刻掩模来更新，因为施加到第一蚀刻掩模或代替第一蚀刻掩模的光致抗蚀剂层被暴露，使得已经被 曝光一次还未完全曝光，并且基于位于光致抗蚀剂层下方并对应于第一蚀刻掩模的反射层另外暴露的区域被完全暴露。

    Trench capacitor and method for manufacturing the same
    34.
    发明授权
    Trench capacitor and method for manufacturing the same 有权
    沟槽电容器及其制造方法

    公开(公告)号：US06674113B2

    公开(公告)日：2004-01-06

    申请号：US10254692

    申请日：2002-09-25

    申请人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Thomas Hecht ,  Jörn Lützen ,  Bernhard Sell

    IPC分类号： H01L2708

    CPC分类号： H01L27/10861

    摘要： A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

    摘要翻译： 沟槽电容器具有布置在电容器电极之间的第一电容器电极，第二电容器电极和电介质。 第一电容器电极具有延伸到基板中的管状结构。 第二电容器电极包括与管状结构的内侧相对的第一部分，其间布置有电介质，第二部分与管状结构的外侧相反，电介质布置 之间。

    CMOS device and method of manufacturing same
    37.
    发明授权
    CMOS device and method of manufacturing same 有权
    CMOS器件及其制造方法

    公开(公告)号：US07663192B2

    公开(公告)日：2010-02-16

    申请号：US12215989

    申请日：2008-06-30

    申请人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

    发明人： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel Aubertine

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

    摘要： A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

    摘要翻译： CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

    Process for producing and removing a mask layer
    38.
    发明授权
    Process for producing and removing a mask layer 有权
    掩模层的制造和除去方法

    公开(公告)号：US07129173B2

    公开(公告)日：2006-10-31

    申请号：US10649411

    申请日：2003-08-27

    申请人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

    发明人： Heike Drummer ,  Franz Kreupl ,  Annette Sänger ,  Manfred Engelhardt ,  Bernhard Sell ,  Peter Thieme

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31053 ,  H01L21/30625 ,  H01L21/31144 ,  H01L21/76819

    摘要： A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

    摘要翻译： 提供半导体衬底，其上布置有第一层，第二层和第三层。 第三层例如是用于图案化第二层的抗蚀剂掩模。 第二层例如是用于图案化第一层的图案化硬掩模。 然后，去除第三层，并沉积第四层。 第四层例如是填充已经形成在第一层中的沟槽的绝缘体。 然后，通过CMP步骤对第四层进行平面化。 继续进行平面化，并且第二层（例如硬掩模）与第四层一起从第一层去除。 第四层保持在布置在第一层中的沟槽中的适当位置。

    Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell
    40.
    发明授权
    Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell 失效
    用于读出，评估和再次读取电荷状态到存储单元中的电路布置

    公开(公告)号：US07009900B2

    公开(公告)日：2006-03-07

    申请号：US10944536

    申请日：2004-09-17

    申请人： Matthias Goldbach ,  Bernhard Sell

    发明人： Matthias Goldbach ,  Bernhard Sell

    IPC分类号： G11C7/00

    CPC分类号： G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/41 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

    摘要： A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).

    摘要翻译： 电路装置包括位线（10），参考位线（12），具有两个交叉耦合CMOS反相器的读出放大器，其在每种情况下都包括n沟道晶体管（20,22）和p沟道 场效应晶体管（30,32），并且在相应的源极端处，两个电压源（40,42），其中连接到n沟道场效应晶体管的电压源（40）可以从 连接到p沟道场效应晶体管（30,32）的电压源（42）可以从上到下的电位驱动。 利用这种电路装置，如果阈值电压（U TH1，U2，...，TH2），则可以在位线（10）上的存储单元（4）中存储三种不同的电荷状态， SUB>）被选择为大于电压下限和下限之间的电压差的一半。 这可以通过生产工程来实现，或者例如通过改变衬底偏置电压来实现。 第三充电状态可用于二进制逻辑或用于检测存储器单元（4）中的缺陷。