摘要:
A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle Θ of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.
摘要:
An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.
摘要:
A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.
摘要:
The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.
摘要:
A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).
摘要:
A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).
摘要:
Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.
摘要:
Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.
摘要:
Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.
摘要:
On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate surface. The covering layer is patterned in a direction which is vertical with respect to the substrate surface by limiting a process quantity of at least one precursor material and/or by temporarily limiting the deposition process, and is formed as a functional layer or mask for subsequent process steps.