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    Non-volatile semiconductor memory with large erase blocks storing cycle counts
    31.
    发明申请
    Non-volatile semiconductor memory with large erase blocks storing cycle counts 有权

    公开(公告)号：US20050102466A1

    公开(公告)日：2005-05-12

    申请号：US11004139

    申请日：2004-12-02

    申请人： Jian Chen ,  Tomoharu Tanaka

    发明人： Jian Chen ,  Tomoharu Tanaka

    IPC分类号： G06F12/00 ,  G11C11/24 ,  G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  H01L27/115

    CPC分类号： G11C11/5635 ,  G06F11/1068 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5646

    摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.

    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance
    32.
    发明申请
    Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
    用于识别具有差的亚阈值斜率或弱跨导的非易失性存储元件的方法

    公开(公告)号：US20050057968A1

    公开(公告)日：2005-03-17

    申请号：US10665685

    申请日：2003-09-17

    申请人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

    发明人： Jeffrey Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

    IPC分类号： G01R31/28 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

    摘要： The present invention presents a number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

    摘要翻译： 本发明提出了用于鉴别具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。

    Charge pump redundancy in a memory
    34.
    发明授权
    Charge pump redundancy in a memory 有权
    存储器中的电荷泵冗余

    公开(公告)号：US09042180B2

    公开(公告)日：2015-05-26

    申请号：US13995166

    申请日：2012-03-25

    申请人： Toru Tanzawa ,  Tomoharu Tanaka

    发明人： Toru Tanzawa ,  Tomoharu Tanaka

    IPC分类号： G11C16/30 ,  G11C5/14 ,  G11C29/00

    CPC分类号： G06F1/32 ,  G11C5/145 ,  G11C16/30 ,  G11C29/702

    摘要： An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.

    摘要翻译： 集成电路包括电路块，以利用来自电源输入和两个或更多个电荷泵阵列的负载电压的负载电流。 电荷泵阵列的输出耦合到电路块的功率输入。 集成电路包括一个或多个可修改的元件以禁用两个或更多个电荷泵阵列中的一个或多个。

    Architecture for 3-D NAND memory
    35.
    发明授权
    Architecture for 3-D NAND memory 有权
    3-D NAND存储器架构

    公开(公告)号：US08964474B2

    公开(公告)日：2015-02-24

    申请号：US13524872

    申请日：2012-06-15

    申请人： Midori Morooka ,  Tomoharu Tanaka

    发明人： Midori Morooka ,  Tomoharu Tanaka

    IPC分类号： G11C16/00

    CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/3427 ,  G11C2213/71

    摘要： Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

    摘要翻译： 描述了包括存储器单元串的堆叠阵列及其操作方法的装置。 装置包括减少几个常用部件的使用的结构，允许给定半导体区域的更大的器件密度和更小的器件尺寸。

    Memory segment accessing in a memory device
    36.
    发明授权
    Memory segment accessing in a memory device 有权
    内存段访问存储设备

    公开(公告)号：US08767470B2

    公开(公告)日：2014-07-01

    申请号：US13564883

    申请日：2012-08-02

    申请人： Tomoharu Tanaka

    发明人： Tomoharu Tanaka

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G06F12/0893 ,  G06F2212/2022 ,  G11C16/0483 ,  G11C16/10 ,  G11C2207/2245 ,  G11C2216/14

    摘要： Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.

    摘要翻译： 通过将所选择的存储器段和任何中间段的某些数据线耦合到相应的数据高速缓冲存储器，基本上同时读取存储器段的位线。 不用于将所选择的段耦合到数据高速缓存的未选择的存储器段的位线可以耦合到它们各自的源极线。

    MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE
    37.
    发明申请
    MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE 有权
    存储器件中的存储器部分访问

    公开(公告)号：US20120294088A1

    公开(公告)日：2012-11-22

    申请号：US13564883

    申请日：2012-08-02

    申请人： Tomoharu Tanaka

    发明人： Tomoharu Tanaka

    IPC分类号： G11C16/04

    CPC分类号： G06F12/0893 ,  G06F2212/2022 ,  G11C16/0483 ,  G11C16/10 ,  G11C2207/2245 ,  G11C2216/14

    摘要： Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple the selected segment to the data caches can be coupled to their respective source lines.

    摘要翻译： 通过将所选择的存储器段和任何中间段的某些数据线耦合到相应的数据高速缓冲存储器，基本上同时读取存储器段的位线。 不用于将所选择的段耦合到数据高速缓存的未选择的存储器段的位线可以耦合到它们各自的源极线。

    Semiconductor memory device
    39.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07952933B2

    公开(公告)日：2011-05-31

    申请号：US12632203

    申请日：2009-12-07

    申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

    发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Toru Tanzawa

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5642

    摘要： A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

    摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的位线，包括预充电电路的读取电路和连接在位线和读取电路之间的第一晶体管，其中第一电压施加到第一晶体管的栅极 当预充电电路对位线进行预充电，并且当读取电路感测到位线的电压变化时，与第一电压不同的第二电压被施加到第一晶体管的栅极。

    Flash memory
    40.
    发明授权
    Flash memory 有权
    闪存

    公开(公告)号：US07908529B2

    公开(公告)日：2011-03-15

    申请号：US12371659

    申请日：2009-02-16

    申请人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

    发明人： Tomoharu Tanaka ,  Noboru Shibata ,  Toru Tanzawa

    IPC分类号： G11C29/00 ,  G11C16/04 ,  H03M13/00

    CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

    摘要翻译： 闪速存储器包括存储器扇区，命令接口，第一信号缓冲器，控制信号生成电路，数据输入缓冲器，纠错电路，地址缓冲器，地址信号生成电路，多个数据存储电路， 和写电路。 命令接口从外部设备接收写入数据输入指令，生成写入数据输入指令信号，并从外部设备接收写入指令，生成写入指令信号。 误差校正电路由写数据输入指令信号激活，以与写使能信​​号同步地接收写入数据，并由写指令信号激活，以产生与控制信号同步的纠错校验数据。