公开(公告)号：US5889310A

公开(公告)日：1999-03-30

申请号：US854088

申请日：1997-05-09

申请人： Tomohide Terashima ,  Kazuhiro Shimizu

发明人： Tomohide Terashima ,  Kazuhiro Shimizu

IPC分类号： H01L27/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7816 ,  H01L27/0629 ,  H01L27/0635 ,  H01L29/1087 ,  H01L29/7801 ,  H01L29/0878 ,  H01L2924/0002

摘要： A high breakdown voltage pch-MOSFET having a breakdown voltage of 150V or more and a control element controlling the same are formed in a common n.sup.- epitaxial layer. Only an n-type region of n.sup.- epitaxial layer is distributed at a region located between the high breakdown voltage pch-MOSFET and the control element and extending along the substrate surface. A semiconductor device thus formed achieves a good throughput and reduces a required chip area.

摘要翻译： 具有150V或更高的击穿电压的高击穿电压pch-MOSFET和控制其的控制元件形成在共同的n-外延层中。 仅n型区域的n型外延层分布在位于高击穿电压pch-MOSFET与控制元件之间的区域上并且沿衬底表面延伸。 这样形成的半导体器件实现了良好的吞吐量并且减少了所需的芯片面积。

公开(公告)号：US5561077A

公开(公告)日：1996-10-01

申请号：US531750

申请日：1995-09-21

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861 ,  H01L21/302

CPC分类号： H01L29/7824 ,  H01L29/0649 ,  H01L29/102 ,  H01L29/402 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78603 ,  H01L29/8611 ,  H01L29/0692 ,  H01L29/0696 ,  Y10S438/981

摘要： A high-breakdown voltage semiconductor device and a fabrication method are disclosed. A dielectric layer (3) dielectrically isolates a semiconductor substrate (1) from a n.sup.- type semiconductor layer (2). An n.sup.+ type semiconductor region (4) having a lower resistance than the n.sup.- type semiconductor layer (2) is formed as if surrounded by a p.sup.+ type semiconductor region (5). The dielectric layer (3) consists of a relatively thick first region (3a) and a relatively thin first region (3b). The n.sup.+ type semiconductor region (4), which is located above the first region (3a), occupies a narrower area than the first region (3a). Thus, by forming the dielectric layer thick immediately under the first semiconductor layer and controlling the thickness of the dielectric layer at other portions, the breakdown voltage of the semiconductor device is improved without curbing RESURF effect.

摘要翻译： 公开了一种高耐压半导体器件和制造方法。 电介质层（3）介电地将半导体衬底（1）与n型半导体层（2）隔离。 形成具有比n型半导体层（2）低的电阻的n +型半导体区域（4），好像被p +型半导体区域（5）包围。 电介质层（3）由较厚的第一区域（3a）和较薄的第一区域（3b）构成。 位于第一区域（3a）上方的n +型半导体区域（4）占据比第一区域（3a）窄的区域。 因此，通过在第一半导体层的正下方形成电介质层，并控制其它部分的电介质层的厚度，可以提高半导体器件的击穿电压，而不会抑制RESURF效应。

公开(公告)号：US5360746A

公开(公告)日：1994-11-01

申请号：US193742

申请日：1994-02-09

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/744 ,  H01L21/329 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L49/00

CPC分类号： H01L29/66356 ,  H01L29/7391 ,  Y10S257/914

摘要： Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.

摘要翻译： 在电极（9）和（10）之间形成有p +衬底（2），具有突出部分（3），n +扩散区域（4）和p +扩散区域（13）的n-外延层（1）。 控制电极（6）形成在突出部（3）和n +扩散区（4）的相对侧的绝缘膜（5）上。 控制电极（6）上的电位随着电极（10）上的电位相对于电极（9）而增加或减小，以在n外延层（1）中产生势垒或电导率调制，由此半导体 设备关闭或打开。 当半导体器件关闭时，引入的空穴通过p +扩散区域（13）被拉出，以便在不改变n +扩散区域（4）的区域的情况下提供小的电阻和短的距离。 这允许半导体器件在低导通电压下具有小的开关损耗和高开关速度。

公开(公告)号：US20150228488A1

公开(公告)日：2015-08-13

申请号：US14427852

申请日：2012-09-26

申请人： Tomohide Terashima ,  Yasuhiro Yoshiura ,  Eiko Otsuki

发明人： Tomohide Terashima ,  Yasuhiro Yoshiura ,  Eiko Otsuki

IPC分类号： H01L21/263 ,  H01J37/30 ,  H01L21/677 ,  H01L21/67 ,  H01L21/68

CPC分类号： H01L21/263 ,  H01J37/30 ,  H01J37/3002 ,  H01J2237/201 ,  H01J2237/202 ,  H01J2237/20221 ,  H01J2237/30455 ,  H01J2237/317 ,  H01L21/67115 ,  H01L21/67718 ,  H01L21/67745 ,  H01L21/6776 ,  H01L21/68

摘要： A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps.

摘要翻译： 根据本发明的半导体器件制造方法包括将多个处理对象布置在与第一托盘相邻的第一托盘和第二托盘上的步骤，多个施加步骤，其中将应用物质应用于多个 通过从第一托盘和第二托盘彼此接触的接触位置正上方形成的施加装置发射施加物质，通过沿着第一方向跨越接触位置摆动施加装置来重复加工物体一定次数 并且通过沿着与第一方向垂直的第二方向移动第一托盘和第二托盘，以及互换步骤，将第一托盘和第二托盘互换在适当位置，而不改变对应于第一托盘和第二托盘的方向 所述第二方向，所述交换步骤在所述多个之中至少执行一次 应用步骤。

公开(公告)号：US08395231B2

公开(公告)日：2013-03-12

申请号：US11831496

申请日：2007-07-31

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H02J7/022 ,  H01L27/0629 ,  H01L27/0635 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/6874 ,  H03K19/017509 ,  Y02B40/90

摘要： A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

摘要翻译： 向充电目标元件提供充电电流的半导体器件包括：第一导电类型的半导体层; 第二导电类型的第一半导体区域形成在半导体层的主表面上并且具有耦合到充电目标元件的第一电极的第一节点和耦合到被提供有电源的电源电位节点的第二节点 电压; 第一导电类型的第二半导体区域形成在距离半导体层一定距离的第一半导体区域的表面中，并且具有耦合到电源电位节点的第三节点; 以及电荷载流子漂移限制部分，其限制载流子从第三节点到半导体层的漂移。

公开(公告)号：US07541248B2

公开(公告)日：2009-06-02

申请号：US11703628

申请日：2007-02-08

申请人： Tetsuya Nitta ,  Tomohide Terashima

发明人： Tetsuya Nitta ,  Tomohide Terashima

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

摘要翻译： 包含具有各自期望的导通电阻和击穿电压的半导体元件的集成半导体器件实现了作为整体的集成半导体元件的适当的特性。 集成半导体器件包括形成在半导体层中并且在源极和漏极之间具有n型半导体源，n型半导体的漏极和p型半导体的栅极的多个半导体元件。 至少一个半导体元件的漏极的预定部分和另一个半导体元件的漏极的预定部分具有彼此不同的杂质浓度。

公开(公告)号：US20070176220A1

公开(公告)日：2007-08-02

申请号：US11622670

申请日：2007-01-12

申请人： Tetsuo Takahashi ,  Tomohide Terashima

发明人： Tetsuo Takahashi ,  Tomohide Terashima

IPC分类号： H01L29/94

CPC分类号： H01L29/7397 ,  H01L21/823878 ,  H01L29/0638 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/41741

摘要： A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

摘要翻译： 一种半导体器件，包括：第一导电类型的半导体衬底; 形成在半导体衬底上的第二导电类型的半导体层; 形成在半导体区域中的沟槽; 沿沟槽的壁表面形成的第一导电类型的沟槽扩散层; 以及埋在沟槽中的掩埋导体，其中绝缘膜进一步设置在沟槽的壁表面和掩埋导体之间。

公开(公告)号：US07186623B2

公开(公告)日：2007-03-06

申请号：US10625733

申请日：2003-07-24

申请人： Tetsuya Nitta ,  Tomohide Terashima

发明人： Tetsuya Nitta ,  Tomohide Terashima

IPC分类号： H01L21/331

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

公开(公告)号：US07071516B2

公开(公告)日：2006-07-04

申请号：US10866677

申请日：2004-06-15

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7395 ,  H01L27/0623 ,  H01L2924/0002 ,  H03K17/0406 ,  H01L2924/00

摘要： A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electrode (15) provided via a gate oxide film (21) on a surface of an N− epitaxial layer (2) between the P diffusion regions (5 and 6). The gate oxide film (21) is formed in a thickness having a gate breakdown voltage higher than the element breakdown voltage of a typical field oxide film and the like.

摘要翻译： 在关断期间，用于在N型IGBT的基极与发射极之间形成短路的PMOS晶体管（Q 2）包括P扩散区（5），P扩散区（6）和导电膜（ 10）和在P扩散区（5和6）之间经由栅极氧化膜（21）设置在N +外延层（2）的表面上的第二栅电极（15）。 栅极氧化膜（21）形成为具有比典型的场氧化物膜等的元件击穿电压高的栅极击穿电压的厚度。

公开(公告)号：US06921945B2

公开(公告)日：2005-07-26

申请号：US10655037

申请日：2003-09-05

申请人： Tomohide Terashima

发明人： Tomohide Terashima

IPC分类号： H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/861 ,  H01L29/868 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/0661 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/8611 ,  H01L29/868

摘要： A semiconductor layer (10) provided on a BOX (buried oxide) layer (2) includes a first P-type region (11), an N+-type region (12), and an N−type region (13) which together form a diode. A plurality of second P-type regions (14) are provided on a bottom part of the semiconductor layer (10). A plurality of insulating oxide films (21) are interposed between the plurality of second P-type regions (14). When the diode is in a reverse-biased state, the second P-type region (14) directly below the N+-type region (12) is approximately the same in potential as the N+-type region (12). The second P-type region (14) will be lower in potential relative to this second P-type region (14) directly below the N+-type region (12), as the second P-type region (14) gets nearer to the first P-type region (11). Electric field concentration can thus be relaxed at an interface between the semiconductor layer (10) and the BOX layer (2), whereby improvement in breakdown voltage of the diode is realized.

摘要翻译： 设置在BOX（掩埋氧化物）层（2）上的半导体层（10）包括第一P型区域（11），N + +型区域（12）和N + 一起形成二极管的类型区域（13）。 多个第二P型区域（14）设置在半导体层（10）的底部。 在多个第二P型区域（14）之间插入有多个绝缘氧化膜（21）。 当二极管处于反向偏置状态时，N + / - 型区域（12）正下方的第二P型区域（14）的电位与N + +区域（12）。 作为第二P型区域，第二P型区域（14）的电位相对于N + +型区域（12）正下方的该第二P型区域（14） 区域（14）越接近第一P型区域（11）。 因此，可以在半导体层（10）和BOX层（2）之间的界面放宽电场浓度，从而实现二极管的击穿电压的提高。