公开(公告)号：US11145733B1

公开(公告)日：2021-10-12

申请号：US17033919

申请日：2020-09-27

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-Hung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Yu-Hsiang Lin ,  Po-Wen Su ,  Chung-Fu Chang ,  Guang-Yu Lo ,  Chun-Tsen Lu

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L21/308 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78

摘要： The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

公开(公告)号：US10475744B2

公开(公告)日：2019-11-12

申请号：US15727380

申请日：2017-10-06

申请人： United Microelectronics Corp.

发明人： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu

IPC分类号： H01L23/532 ,  H01L21/02 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  B82Y99/00

摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

公开(公告)号：US10446448B2

公开(公告)日：2019-10-15

申请号：US16175776

申请日：2018-10-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC分类号： H01L29/06 ,  H01L21/8234

摘要： A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

公开(公告)号：US20190074250A1

公开(公告)日：2019-03-07

申请号：US15727380

申请日：2017-10-06

申请人： United Microelectronics Corp.

发明人： Kuan-Hung Chen ,  Rung-Yuan Lee ,  Chun-Tsen Lu

IPC分类号： H01L23/532 ,  H01L21/762 ,  H01L21/02

摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

公开(公告)号：US20190067118A1

公开(公告)日：2019-02-28

申请号：US16175776

申请日：2018-10-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Hao Lin ,  Hsin-Yu Chen ,  Chun-Tsen Lu ,  Shou-Wei Hsieh

IPC分类号： H01L21/8234 ,  H01L21/02

CPC分类号： H01L21/823462 ,  H01L21/823431

摘要： A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.

公开(公告)号：US10192826B2

公开(公告)日：2019-01-29

申请号：US15853978

申请日：2017-12-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC分类号： H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

摘要： A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US10008581B2

公开(公告)日：2018-06-26

申请号：US14840041

申请日：2015-08-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  C22C32/00 ,  H01L29/51 ,  H01L21/28 ,  B32B1/00

CPC分类号： H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

公开(公告)号：US09966263B1

公开(公告)日：2018-05-08

申请号：US15587228

申请日：2017-05-04

申请人： United Microelectronics Corp.

发明人： Kun-Ju Li ,  Li-Chieh Hsu ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Chih-Hsun Lin ,  Hsin-Jung Liu

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

摘要： A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.

公开(公告)号：US20160351674A1

公开(公告)日：2016-12-01

申请号：US15232796

申请日：2016-08-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC分类号： H01L29/423 ,  H01L21/66 ,  H01L29/51 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321

CPC分类号： H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.

摘要翻译： 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。 还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09502303B2

公开(公告)日：2016-11-22

申请号：US14682265

申请日：2015-04-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Chun-Tsen Lu ,  Wen-Chin Lin ,  Fu-Shou Tsai

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/285

CPC分类号： H01L21/823475 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871

摘要： A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

摘要翻译： 提供一种制造半导体器件的方法。 提供其上形成有绝缘体的基板，其中绝缘体具有多个沟槽，并且相邻的沟槽彼此间隔开。 在绝缘体的上表面和沟槽的侧壁中形成阻挡层，并且阻挡层包括对应于沟槽的悬垂部分。 种子层形成在阻挡层上。 然后，除去形成在阻挡层的上表面上的种子层的上部。 去除阻挡层的上部以暴露绝缘体的上表面。 之后，导体沿种子层沉积以填充沟槽，其中导体的顶表面基本上与绝缘体的上表面对齐。