公开(公告)号：US09530646B2

公开(公告)日：2016-12-27

申请号：US14629491

申请日：2015-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  An-Chi Liu ,  Chih-Wei Wu ,  Jyh-Shyang Jenq ,  Shih-Fang Hong ,  En-Chiuan Liou ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Mei-Chen Chen ,  Chia-Hsun Tseng

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/66 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L22/12

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，提供具有多个心轴图案的图案化的硬掩模层。 接下来，通过图案化的硬掩模在基板上形成多个第一心轴。 接下来，执行至少一个侧壁图像传送（SIT）处理。 最后，在基板上形成多个散热片，其中每个翅片具有预定的临界尺寸（CD），并且每个心轴图案具有比预定CD大5-8倍的CD。

公开(公告)号：US09490341B2

公开(公告)日：2016-11-08

申请号：US14704994

申请日：2015-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy gate is formed on the substrate and the transistor is embedded in an interlayer dielectric (ILD) layer. A first removal process is performed to remove a portion of the dummy gate to form a first recess in the transistor. An etching process is subsequently performed to remove a portion of the ILD layer to widen the first recess and to form a widened first recess. A second removal process is subsequently performed to remove the dummy gate entirely and to form a second recess in the transistor. A metal gate is formed in the second recess and followed by forming an insulating cap layer on the metal gate.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供基板。 在衬底上形成至少包括伪栅极的晶体管，并且将晶体管嵌入在层间电介质层（ILD）层中。 执行第一去除处理以去除伪栅极的一部分以在晶体管中形成第一凹部。 随后进行蚀刻处理以去除ILD层的一部分以加宽第一凹部并形成加宽的第一凹部。 随后执行第二去除处理以完全去除伪栅极并在晶体管中形成第二凹槽。 在第二凹部中形成金属栅极，然后在金属栅极上形成绝缘盖层。

公开(公告)号：US20160306274A1

公开(公告)日：2016-10-20

申请号：US14685615

申请日：2015-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Hsun Tseng ,  Tuan-Yen Yu ,  Po-Tsang Chen ,  Yi-Ting Chen

IPC: G03F1/76 ,  H01L21/033

CPC classification number: G03F1/76 ,  G03F1/54 ,  G03F1/58 ,  G03F1/70 ,  G03F1/72 ,  G03F1/80 ,  H01L21/0337

Abstract: A manufacturing method of a pattern transfer mask includes the following steps. A basic mask is provided. The basic mask includes a plurality of patterns formed by a patterned absorber layer on a substrate according to a first writing layout. A photolithographic process is then performed by the basic mask to obtain individual depth of focus (iDoF) ranges of each of the patterns and a usable depth of focus (UDoF) range of the patterns. At least one constrain pattern dominating the UDoF range is selected from the patterns in the basic mask. The rest of the patterns except the constrain pattern are non-dominating patterns. A second writing layout is then generated for reducing a thickness of the patterned absorber layer in the constrain pattern or in the non-dominating patterns.

Abstract translation: 图案转印掩模的制造方法包括以下步骤。 提供基本的面具。 基本掩模包括根据第一写入布局在基板上由图案化的吸收层形成的多个图案。 然后通过基本掩模执行光刻处理，以获得每种图案的单独焦点深度（iDoF）范围和图案的可用深度（UDoF）范围。 从基本掩码中的图案中选择至少一个主导UDoF范围的约束图案。 除了约束模式之外的其余模式是非主导模式。 然后生成第二写入布局以减小约束图案中的图案化吸收层的厚度或以非主导图案的方式。

公开(公告)号：US09466564B1

公开(公告)日：2016-10-11

申请号：US14692762

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L23/522 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 栅极结构上的第一个硬掩模; 以及栅极结构上的第二硬掩模，其中所述第一硬掩模与所述第二硬掩模的两侧相邻，并且所述第一硬掩模和所述第一硬掩模包括氮化硅。

公开(公告)号：US20160276260A1

公开(公告)日：2016-09-22

申请号：US14682124

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

Abstract translation: 公开了一种用于制造金属互连结构的方法。 该方法包括以下步骤：提供其上具有第一金属间电介质（IMD）层的衬底; 在第一IMD层中形成金属互连; 去除第一IMD层的一部分; 形成邻近所述金属互连的间隔物; 并且使用间隔物作为掩模来去除第一IMD层的一部分，以在第一IMD层中形成开口。

公开(公告)号：US09448471B2

公开(公告)日：2016-09-20

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US09410902B1

公开(公告)日：2016-08-09

申请号：US14703890

申请日：2015-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yi-Jing Wang

IPC: G01B11/14 ,  G01N21/95 ,  G01B11/27 ,  G01N21/88

CPC classification number: G01N21/9501 ,  G01B11/27 ,  G01N21/8806 ,  G01N2021/8825 ,  G03F7/70633

Abstract: An overlay measurement method includes providing three predetermined patterns, including a first predetermined pattern, a second predetermined pattern and a third predetermined pattern. An inspection process is then performed on said three predetermined patterns, to obtain three image points, including a first image point, a second image point and a third image point respectively. Next, a defining process is performed to define a default position, and a calculating process is performed to obtain a real offset value x=(p−q)*(c−a)/(a−b)+p.

Abstract translation: 覆盖测量方法包括提供包括第一预定图案，第二预定图案和第三预定图案的三个预定图案。 然后对所述三个预定图案执行检查处理，以分别获得包括第一图像点，第二图像点和第三图像点的三个图像点。 接下来，执行定义处理以定义默认位置，并且执行计算处理以获得实际偏移值x =（p-q）*（c-a）/（a-b）+ p。

公开(公告)号：US09406521B1

公开(公告)日：2016-08-02

申请号：US14793692

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L21/308 ,  H01L27/088 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括衬底，多个鳍状结构和绝缘层。 衬底具有鳍状场效应晶体管（finFET）区域，第一区域，第二区域和第三区域。 第一区域，第二区域和第三区域分别具有第一表面，第二表面和第三表面，其中第一表面相对高于第二表面，而第二表面相对高于第三表面。 鳍状结构设置在鳍状场效应晶体管区域的表面上。 绝缘层覆盖第一表面，第二表面和第三表面。

公开(公告)号：US08928112B2

公开(公告)日：2015-01-06

申请号：US14337170

申请日：2014-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/00 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。

公开(公告)号：US20140332920A1

公开(公告)日：2014-11-13

申请号：US14337170

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Jia-Rong Wu

IPC: H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76235 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure includes an upper insulating portion and a lower insulating portion, where the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. Apart of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 除了第一绝缘体和第二绝缘体之间的缓冲层界面之外，缓冲层的外侧壁和第一绝缘体的侧壁被平整。