公开(公告)号：US12057401B2

公开(公告)日：2024-08-06

申请号：US18226784

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US20230327000A1

公开(公告)日：2023-10-12

申请号：US18208895

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/66545 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L29/785 ,  H01L21/31116

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US10658369B2

公开(公告)日：2020-05-19

申请号：US16027356

申请日：2018-07-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kun-Hsin Chen ,  Hsuan-Tung Chu ,  Tsuo-Wen Lu ,  Po-Chun Chen

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner, wherein the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.

公开(公告)号：US20190164977A1

公开(公告)日：2019-05-30

申请号：US16226648

申请日：2018-12-20

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US09735235B2

公开(公告)日：2017-08-15

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

公开(公告)号：US09685533B1

公开(公告)日：2017-06-20

申请号：US15049133

申请日：2016-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

公开(公告)号：US20140295629A1

公开(公告)日：2014-10-02

申请号：US13850887

申请日：2013-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Hsin-Kuo Hsu ,  Yu-Shu Lin ,  Szu-Hao Lai ,  Ming-Hua Chang

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  Y10S438/938

Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.

Abstract translation: 公开了一种形成半导体器件的方法。 至少一个栅极结构设置在衬底上，其中栅极结构包括形成在栅极的侧壁上的第一间隔物。 在覆盖栅极结构的衬底上沉积第一一次性间隔物层。 第一一次性间隔物材料层被蚀刻以在第一间隔物上形成第一一次性间隔物。 在覆盖栅极结构的衬底上沉积第二一次性间隔物材料层。 蚀刻第二一次性间隔材料层以在第一一次性间隔件上形成第二一次性间隔件。 通过使用第一和第二一次性间隔件作为掩模来去除衬底的一部分，以在栅极结构旁边的衬底中形成两个凹部。 在凹部中形成应力诱导层。

公开(公告)号：US20140199854A1

公开(公告)日：2014-07-17

申请号：US13742467

申请日：2013-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02

CPC classification number: H01L21/02312 ,  C23C16/02 ,  C23C16/45546 ,  C23C16/4583 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02304

Abstract: A method of forming a film is provided. The method includes at least the following steps. A first substrate and a second substrate are provided in a batch processing system, wherein a first surface of the first substrate is adjacent to a second surface of the second substrate, the first surface of the first substrate has a first surface condition, the second surface of the second substrate has a second surface condition, and the first surface condition is different from the second surface condition. A pretreatment gas is provided to the surfaces of the substrates for transforming the first surface condition and the second surface condition to a third surface condition. A reaction gas is provided to form the film on the surfaces, having the third surface condition, of the substrates.

Abstract translation: 提供了一种形成膜的方法。 该方法至少包括以下步骤。 第一基板和第二基板设置在间歇处理系统中，其中第一基板的第一表面与第二基板的第二表面相邻，第一基板的第一表面具有第一表面状态，第二表面 所述第二基板具有第二表面状态，所述第一表面状态与所述第二表面状态不同。 将预处理气体提供到基板的表面，用于将第一表面状态和第二表面状态转换成第三表面状态。 提供反应气体以在具有第三表面状态的基底的表面上形成膜。

公开(公告)号：US20240421213A1

公开(公告)日：2024-12-19

申请号：US18813074

申请日：2024-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.

公开(公告)号：US11508832B2

公开(公告)日：2022-11-22

申请号：US17209244

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Tsuo-Wen Lu ,  Chia-Ming Kuo ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750° C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.