公开(公告)号：US10056463B2

公开(公告)日：2018-08-21

申请号：US15628592

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11585

CPC classification number: H01L29/516 ,  H01L27/11585 ,  H01L29/40111 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7869

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

公开(公告)号：US09887238B1

公开(公告)日：2018-02-06

申请号：US15413349

申请日：2017-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L45/00 ,  H01L21/8234 ,  H01L27/24 ,  H01L29/786

CPC classification number: H01L27/2436 ,  H01L21/82345 ,  H01L29/7869 ,  H01L45/065 ,  H01L45/122 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608

Abstract: A semiconductor device and a method for fabricating the semiconductor device have been provided. The method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.

公开(公告)号：US20170154887A1

公开(公告)日：2017-06-01

申请号：US15432165

申请日：2017-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US20170125402A1

公开(公告)日：2017-05-04

申请号：US14956398

申请日：2015-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Chen-Bin Lin ,  Su Xing ,  Chi-Chang Shuai ,  Chung-Yuan Lee

IPC: H01L27/06 ,  H01L29/861 ,  H01L49/02 ,  H01L29/22 ,  H01L29/06 ,  H01L23/535 ,  H01L29/10 ,  H01L29/24

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0727 ,  H01L28/00 ,  H01L28/40 ,  H01L29/0603 ,  H01L29/1079 ,  H01L29/22 ,  H01L29/24 ,  H01L29/861

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

公开(公告)号：US09607982B1

公开(公告)日：2017-03-28

申请号：US15209771

申请日：2016-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang

IPC: H01L27/06 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8249 ,  H01L27/02 ,  H01L29/49 ,  H01L29/26

CPC classification number: H01L27/0635 ,  G05F1/56 ,  H01L21/8249 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/088 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/26 ,  H01L29/41708 ,  H01L29/4966 ,  H01L29/66234 ,  H01L29/735

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a bipolar junction transistor (BJT) is formed on the substrate, a metal-oxide semiconductor (MOS) transistor is formed on the substrate and electrically connected to the BJT, a resistor is formed on the substrate and electrically connected to the MOS transistor, a dielectric layer is formed on the substrate to cover the BJT, the MOS transistor, and the resistor, and an oxide-semiconductor field-effect transistor (OS-FET) is formed on the dielectric layer and electrically connected to the MOS transistor and the resistor.

公开(公告)号：US20230163184A1

公开(公告)日：2023-05-25

申请号：US17752888

申请日：2022-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Purakh Raj Verma ,  Rudy Octavius Sihombing ,  Shyam Parthasarathy ,  JINYU LIAO

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L29/41758 ,  H01L29/0653 ,  H01L21/823418 ,  H01L21/823481

Abstract: A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

公开(公告)号：US20220415831A1

公开(公告)日：2022-12-29

申请号：US17383290

申请日：2021-07-22

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

公开(公告)号：US20220216345A1

公开(公告)日：2022-07-07

申请号：US17705380

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20210210605A1

公开(公告)日：2021-07-08

申请号：US17191720

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Su Xing

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66

Abstract: An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.

公开(公告)号：US20210175371A1

公开(公告)日：2021-06-10

申请号：US16739022

申请日：2020-01-09

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.