公开(公告)号：US20130320559A1

公开(公告)日：2013-12-05

申请号：US13900081

申请日：2013-05-22

Applicant: XINTEC INC.

Inventor： Yu-Ting HUANG ,  Shu-Ming CHANG ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: B81B7/00

CPC classification number: B81B7/0077 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/64 ,  H01L23/481 ,  H01L23/498 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，包括：第一半导体衬底; 设置在所述第一半导体衬底上的第二半导体衬底，其中所述第二半导体衬底包括下半导体层，上半导体层和位于所述下半导体层和所述上半导体层之间的绝缘层，以及所述下半导体 层与第一半导体衬底上的至少焊盘电接触; 信号导通结构，设置在所述第一半导体衬底的下表面上，其中所述信号导电结构电连接到所述第一半导体衬底上的信号焊盘; 以及导电层，其设置在所述第二半导体衬底的所述上半导体层上并与所述下半导体层的与所述第一半导体衬底上的所述至少一个焊盘电接触的部分电接触。

公开(公告)号：US20220219970A1

公开(公告)日：2022-07-14

申请号：US17711067

申请日：2022-04-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.

公开(公告)号：US20210269303A1

公开(公告)日：2021-09-02

申请号：US17184443

申请日：2021-02-24

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20180358398A1

公开(公告)日：2018-12-13

申请号：US15996841

申请日：2018-06-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L24/02 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14632 ,  H01L27/14678 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/13024

Abstract: A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.

公开(公告)号：US20160351608A1

公开(公告)日：2016-12-01

申请号：US15163625

申请日：2016-05-24

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Chi-Chang LIAO ,  Tsang-Yu LIU

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14698 ,  H01L2224/16 ,  H01L2924/16235

Abstract: A chip package includes a substrate, a conductive layer and a plurality of thermal dissipation connections. The substrate includes a light-sensing region and has an upper surface and a lower surface opposite to each other. The conductive layer is disposed at the lower surface of the substrate and includes a light-shielding dummy conductive layer substantially aligned with the light-sensing region. The thermal dissipation connections are disposed beneath the lower surface of the substrate.

Abstract translation: 芯片封装包括衬底，导电层和多个散热连接。 基板包括感光区域，并且具有彼此相对的上表面和下表面。 导电层设置在基板的下表面，并且包括基本上与光感测区域对准的遮光虚拟导电层。 散热连接设置在基板的下表面之下。

公开(公告)号：US20160211297A1

公开(公告)日：2016-07-21

申请号：US15001065

申请日：2016-01-19

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chia-Ming CHENG

IPC: H01L27/146

Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

Abstract translation: 芯片封装的制造方法包括以下步骤。 透光基板结合到晶片的第一表面，使得透光基板和晶片之间的阻挡元件覆盖晶片的导电焊盘。 蚀刻晶片背离第一表面的第二表面，使得在晶片中同时形成中空区域和选择性地与中空区域连通的沟槽。 蚀刻导电焊盘上的第一隔离层，以通过中空区域露出导电焊盘。

公开(公告)号：US20160171273A1

公开(公告)日：2016-06-16

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Hsing-Lung SHEN

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: G06K9/0002 ,  G06F3/0414 ,  G06K9/00013 ,  H01L2224/141 ,  H01L2224/16225

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

Abstract translation: 芯片封装包括基板，电容感测层和计算芯片。 基板具有与第一表面相对的第一表面和第二表面，并且电容感测层设置在第二表面上方并且具有与第二表面相对的第三表面，电容感测层包括多个电容感测电极 和多根金属线。 电容感测电极位于第二表面上，并且金属线在电容感测电极上。 计算芯片设置在第三表面上方并电连接到电容感测电极。

公开(公告)号：US20160043123A1

公开(公告)日：2016-02-11

申请号：US14819138

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.

Abstract translation: 半导体结构包括芯片，透光板，间隔物和遮光层。 芯片具有图像传感器，与第一表面相对的第一表面和第二表面。 图像传感器位于第一个表面。 透光板设置在第一表面上并覆盖图像传感器。 间隔物在透光板和第一表面之间，并且围绕图像传感器。 遮光层位于间隔件和图像传感器之间的第一表面上。

公开(公告)号：US20150287619A1

公开(公告)日：2015-10-08

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L21/67 ,  H01L21/78 ,  B26F3/00 ,  H01L21/683 ,  H01L21/30

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

Abstract translation: 本发明的一个实施例提供了一种分离装置，用于分离堆叠制品，例如具有感测功能的半导体芯片封装，包括基板和形成在基板上的盖层。 分离装置包括：真空喷嘴头，包括具有顶表面和底表面的吸盘，穿过吸垫的顶表面和底表面的通孔;以及将通孔连接到真空泵的中空真空管 ; 位于真空喷嘴头下方并基本上与吸盘对准的阶段; 连接到真空喷嘴头以将真空喷嘴头向上或向下提升的控制装置; 以及第一切割器，其包括连接到第一切割体的第一切割体和第一切割刀。 在真空泵开始真空吸入中空真空管和通孔中的空气之后，盖层被吸盘的底面压紧并被真空喷嘴头的吸盘吸入。 然后，第一切割器切入基板和盖层之间的界面，并且通过真空喷嘴头的吸力和由真空喷嘴头的向上运动产生的提升力将盖子与基板分离。

公开(公告)号：US20150284244A1

公开(公告)日：2015-10-08

申请号：US14676738

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: B81C1/00 ,  H01L21/683 ,  H01L23/00 ,  H01L27/146 ,  H01L21/78

CPC classification number: B81C1/00896 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L24/11 ,  H01L24/43 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/05432 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

Abstract translation: 提供了一种形成芯片封装的方法。 该方法包括提供衬底和覆盖层，其中衬底在其中邻近衬底的表面具有感测装置。 封盖层通过粘合剂层附接到基底的表面，其中粘合剂层覆盖感测装置。 沿着形成单个芯片封装的方向在衬底，粘合剂层和覆盖层上进行切割工艺。