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109 条记录 (耗时 0.021 秒)

    Output buffer circuit having output bouncing controlled circuits
    32.
    发明授权
    Output buffer circuit having output bouncing controlled circuits 失效
    输出缓冲电路，具有输出弹跳控制电路

    公开(公告)号：US5323070A

    公开(公告)日：1994-06-21

    申请号：US821941

    申请日：1992-01-17

    申请人： Masahiro Ueda ,  Ichiro Tomioka

    发明人： Masahiro Ueda ,  Ichiro Tomioka

    IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/092

    CPC分类号： H03K19/01721 ,  H03K19/00361 ,  H03K19/09448

    摘要： A first output buffer having a large current driving capability and a second output buffer having a small current driving capability are connected in parallel between an input terminal and an external lead. The first and second output buffers each includes two CMOS inverters connected in series between the input terminal and the external lead. The P-channel and N-channel MOSFETs of the two CMOS inverters in the second output buffer have gate widths smaller than each of the P-channel and N-channel MOSFETs, respectively, of the two CMOS inverters in the first output buffer. Also disclosed is an output buffer having P-channel and N-channel MOSFETs arranged as a CMOS inverter, but with a base of a first bipolar transistor connected to a source of the N-channel MOSFET. An emitter of the first bipolar transistor is connected to ground and its collector is connected to an output of the output buffer. A base of a second bipolar transistor is connected to an output of the CMOS inverter and its emitter is connected to the output of the output buffer. An input of the output buffer is supplied to an input of the CMOS inverter. Another transistor is connected between the output of the output buffer and ground and is responsive to the input of the output buffer.

    摘要翻译： 具有大电流驱动能力的第一输出缓冲器和具有小电流驱动能力的第二输出缓冲器并联连接在输入端和外部引线之间。 第一和第二输出缓冲器各自包括串联连接在输入端和外部引线之间的两个CMOS反相器。 第二输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET分别具有比第一输出缓冲器中的两个CMOS反相器的P沟道和N沟道MOSFET中的每一个的栅极宽度小的栅极宽度。 还公开了具有布置为CMOS反相器但具有连接到N沟道MOSFET的源极的第一双极晶体管的基极的P沟道和N沟道MOSFET的输出缓冲器。 第一双极晶体管的发射极连接到地，其集电极连接到输出缓冲器的输出端。 第二双极晶体管的基极连接到CMOS反相器的输出，其发射极连接到输出缓冲器的输出端。 输出缓冲器的输入被提供给CMOS反相器的输入。 另一个晶体管连接在输出缓冲器的输出和地之间，并响应于输出缓冲器的输入。

    Semiconductor integrated circuit device for forming logic circuit including resistance element connected to bipolar transistor with smaller occupied area
    33.
    发明授权
    Semiconductor integrated circuit device for forming logic circuit including resistance element connected to bipolar transistor with smaller occupied area 失效
    用于形成逻辑电路的半导体集成电路器件，包括连接到具有较小占用面积的双极晶体管的电阻元件

    公开(公告)号：US5278436A

    公开(公告)日：1994-01-11

    申请号：US739144

    申请日：1991-08-01

    申请人： Katsushi Asahina ,  Masahiro Ueda

    发明人： Katsushi Asahina ,  Masahiro Ueda

    IPC分类号： H01L21/8249 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H01L27/02 ,  H01L27/10

    CPC分类号： H01L27/11896

    摘要： Disclosed is an improved Bi-CMOS gate array for increasing integration density. The gate array includes a predetermined region for forming PMOS transistors, a predetermined region for forming bipolar transistors, a predetermined region for forming resistance elements, and a predetermined region for forming NMOS transistors. The resistance element region is formed adjacent to the bipolar transistor region, and, therefore, it is not necessary to provide any interconnection for forming a logic circuit including the resistance element connected to the bipolar transistor. An area occupied by interconnections on the semiconductor substrate is thus reduced, and, therefore the integration density is increased.

    摘要翻译： 公开了一种用于增加集成密度的改进的Bi-CMOS门阵列。 栅极阵列包括用于形成PMOS晶体管的预定区域，用于形成双极晶体管的预定区域，用于形成电阻元件的预定区域，以及用于形成NMOS晶体管的预定区域。 电阻元件区域形成为与双极晶体管区域相邻，因此，不需要提供用于形成包括连接到双极晶体管的电阻元件的逻辑电路的任何互连。 因此，半导体基板上的互连占有的面积减小，因此集成密度增加。

    High speed BiCMOS logic circuit
    34.
    发明授权
    High speed BiCMOS logic circuit 失效
    高速BICMOS逻辑电路

    公开(公告)号：US5164617A

    公开(公告)日：1992-11-17

    申请号：US703870

    申请日：1991-05-23

    申请人： Toshiaki Hanibuchi ,  Masahiro Ueda

    发明人： Toshiaki Hanibuchi ,  Masahiro Ueda

    IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/04 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944

    CPC分类号： H01L27/0623 ,  H03K19/0136 ,  H03K19/09448

    摘要： A signal applied through a signal input terminal is logically processed by a logic circuit such as a CMOS inverter and the processed signal is supplied from the signal output terminal. A pinch resistor has a resistance value controlled in accordance with a variation of a voltage at the signal output terminal. Specifically, the pinch resistor has a higher resistance value at an initial stage in the switching operation in which an output from the logic circuit lowers from a logical high level to a logical low level, and supplies a large base current to a bipolar transistor. At a later stage in the switching operation, the pinch resistor has a small resistance value, so that a residual charge in the signal output terminal and a base charge in the bipolar transistor are rapidly emitted through the pinch resistor. Thus, the resistance value of the pinch resistor is always maintained at an optimum value, which increases a speed of the switching operation of the logic circuit.

    摘要翻译： 通过信号输入端施加的信号由CMOS反相器等逻辑电路进行逻辑处理，从信号输出端提供处理后的信号。 夹持电阻器具有根据信号输出端子处的电压变化而控制的电阻值。 具体地说，在逻辑电路的输出从逻辑高电平降低到逻辑低电平的开关动作中，钳位电阻在初始阶段具有较高的电阻值，并向双极型晶体管提供较大的基极电流。 在开关操作的稍后阶段，夹持电阻器具有小的电阻值，使得信号输出端子中的剩余电荷和双极晶体管中的基极电荷通过夹持电阻器快速发射。 因此，夹持电阻器的电阻值始终保持在最佳值，这增加了逻辑电路的开关操作速度。

    Selective light transmitting window glazings and methods of design and manufacture
    36.
    发明授权
    Selective light transmitting window glazings and methods of design and manufacture 有权
    选择性透光窗玻璃及其设计制造方法

    公开(公告)号：US09365449B2

    公开(公告)日：2016-06-14

    申请号：US13421947

    申请日：2012-03-16

    申请人： Masahiro Ueda

    发明人： Masahiro Ueda

    IPC分类号： G02B27/00 ,  C03C17/00 ,  G02B5/02 ,  B60J1/00

    CPC分类号： C03C17/00 ,  B60J1/008 ,  C03C2217/70 ,  G02B5/0278

    摘要： Technologies are generally described for designing a window glazing for a particular geographical location. In some examples, a window glazing can be designed to selectively block sunlight from entering the window during summer when it may be desirable to have inside temperatures substantially lower than outside temperatures. The glazing can also be designed to selectively allow sunlight to enter the window during winter months when heat from sunlight may be desirable to raise indoor temperatures. The glazing can be prepared from a transparent material that can allow substantially full transmission of sunlight.

    摘要翻译： 通常描述技术用于为特定地理位置设计窗玻璃。 在一些示例中，可以设计窗玻璃以在夏季期间选择性地阻挡太阳光进入窗户，当期望内部温度显着低于外部温度时。 玻璃也可以设计成在冬季从阳光下升热可以提高室内温度，从而选择性地允许阳光进入窗户。 玻璃可以由透明材料制成，可以实现充分的太阳光透射。

    Targeted separation of cultured cells
    38.
    发明授权
    Targeted separation of cultured cells 有权
    培养细胞的靶向分离

    公开(公告)号：US08951765B2

    公开(公告)日：2015-02-10

    申请号：US12624972

    申请日：2009-11-24

    申请人： Masahiro Ueda

    发明人： Masahiro Ueda

    IPC分类号： C12N13/00 ,  C12M1/00

    CPC分类号： C12M47/04 ,  C12M47/02

    摘要： Embodiments described herein relate to separating and/or concentrating target cells from a carrier fluid that may include other non-target cells. Embodiments include a cell separator with a flow surface having indentations formed thereon. The indentations are configured to capture target cells by physical and/or chemical interactions. The indentations may also include a layer of support molecules that assist in releasing captured cells for collection.

    摘要翻译： 本文所述的实施方案涉及从可能包括其它非靶细胞的载体流体中分离和/或浓集靶细胞。 实施例包括具有形成在其上的凹陷的流动面的细胞分离器。 这些凹陷配置为通过物理和/或化学相互作用捕获靶细胞。 凹陷还可以包括有助于释放被捕获的细胞进行收集的支撑分子层。

    Solid electrolytic capacitor and method of manufacturing solid electrolytic capacitor
    39.
    发明授权
    Solid electrolytic capacitor and method of manufacturing solid electrolytic capacitor 有权
    固体电解电容器及固体电解电容器的制造方法

    公开(公告)号：US08654510B2

    公开(公告)日：2014-02-18

    申请号：US13035092

    申请日：2011-02-25

    申请人： Masahiro Ueda ,  Ayao Moriyama

    发明人： Masahiro Ueda ,  Ayao Moriyama

    IPC分类号： B01J13/00 ,  H01G9/00 ,  H01B1/00

    CPC分类号： H01G9/025 ,  H01G9/022

    摘要： A solid electrolytic capacitor includes a solid electrolytic capacitor element having an anode element having a dielectric film formed on a surface thereof and a conductive polymer layer formed on the anode element, an ionic liquid composed of an anion component and a cation component is present in the conductive polymer layer, and the cation component contains a cation having two or more ether linkages.

    摘要翻译： 固体电解电容器包括固体电解电容器元件，其具有在其表面上形成有电介质膜的阳极元件和形成在阳极元件上的导电聚合物层，由阴离子成分和阳离子成分组成的离子液体存在于 导电聚合物层，并且阳离子组分含有具有两个或更多个醚键的阳离子。