Light-emitting diode and method for fabrication thereof
    32.
    发明授权
    Light-emitting diode and method for fabrication thereof 有权
    发光二极管及其制造方法

    公开(公告)号:US08217405B2

    公开(公告)日:2012-07-10

    申请号:US12952427

    申请日:2010-11-23

    IPC分类号: H01L21/00

    摘要: A light-emitting diode includes a substrate, a compound semiconductor layer including a p-n junction-type light-emitting part formed on the substrate, an electric conductor disposed on the compound semiconductor layer and formed of an electrically conductive material optically transparent to the light emitted from the light-emitting part and a high resistance layer possessing higher resistance than the electric conductor and provided in the middle between the compound semiconductor layer and the electric conductor. In the configuration of a light-emitting diode lamp, the electric conductor and the electrode disposed on the semiconductor layer on the side opposite to the electric conductor across the light-emitting layer are made to assume an equal electric potential by means of wire bonding. The light-emitting diode abounds in luminance and excels in electrostatic breakdown voltage.

    摘要翻译: 发光二极管包括基板,包括形成在基板上的pn结型发光部的化合物半导体层,配置在化合物半导体层上并由对所发出的光进行光学透明化的导电材料形成的导体 来自发光部分和具有比导体更高的电阻并且设置在化合物半导体层和电导体之间的中间的高电阻层。 在发光二极管灯的构造中,通过引线接合使设置在跨越发光层的与导电体相反一侧的半导体层上的电导体和电极呈现相等的电位。 发光二极管的亮度大,静电击穿电压也好。

    Techniques and devices for characterizing spatially non-uniform curvatures and stresses in thin-film structures on substrates with non-local effects

    公开(公告)号:US20060276977A1

    公开(公告)日:2006-12-07

    申请号:US11432663

    申请日:2006-05-10

    IPC分类号: G01L1/00

    CPC分类号: G01L5/0047 Y10S438/936

    摘要: Techniques and devices are described to use spatially-varying curvature information of a layered structure to determine stresses at each location with non-local contributions from other locations of the structure. For example, a local contribution to stresses at a selected location on a layered structure formed on a substrate is determined from curvature changes at the selected location and a non-local contribution to the stresses at the selected location is also determined from curvature changes at all locations across the layered structure. Next, the local contribution and the non-local contribution are combined to determine the total stresses at the selected location. Techniques and devices for determining a misfit strain between a film and a substrate on which the film is deposited are also described.

    Bipolar transistor and fabrication method thereof
    34.
    发明授权
    Bipolar transistor and fabrication method thereof 失效
    双极晶体管及其制造方法

    公开(公告)号:US06939772B2

    公开(公告)日:2005-09-06

    申请号:US10882220

    申请日:2004-07-02

    摘要: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

    摘要翻译: 通过在Si衬底上的集电极层102上的外延生长,顺序地生长SiGe间隔层151,包括硼的梯度SiGe基极层152和Si覆盖层153。 在Si覆盖层153上形成有第二沉积氧化物膜112,其具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115,发射极扩散层153a 通过将磷扩散到Si覆盖层153中而形成。当Si覆盖层153生长时,通过使Si覆盖层153仅通过原位掺杂在其上部包含硼而形成, 层154变窄,复合电流降低,从而可以提高电流特性的线性。

    Field effect transistor and method of fabrication
    37.
    发明授权
    Field effect transistor and method of fabrication 有权
    场效应晶体管及其制造方法

    公开(公告)号:US06825506B2

    公开(公告)日:2004-11-30

    申请号:US10306640

    申请日:2002-11-27

    IPC分类号: H01L31072

    摘要: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

    摘要翻译: 本发明是一种新颖的场效应晶体管,其具有由形成在绝缘基板上的窄带隙半导体膜形成的沟道区。 在窄带隙半导体膜上形成栅极电介质层。 然后在栅极电介质上形成栅电极。 由宽带隙半导体膜或金属形成的一对源极/漏极区域形成在栅电极的相对侧并与低带隙半导体膜相邻。

    Masking method for producing semiconductor components, particularly a BH laser diode
    38.
    发明申请
    Masking method for producing semiconductor components, particularly a BH laser diode 有权
    用于制造半导体元件,特别是BH激光二极管的掩模方法

    公开(公告)号:US20020182879A1

    公开(公告)日:2002-12-05

    申请号:US10052950

    申请日:2002-01-18

    摘要: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.

    摘要翻译: 一种方法产生用于半导体部件,特别是BH激光二极管的结构,其中在掩模步骤中将掩模材料施加到样品。 蚀刻步骤中的蚀刻速率取决于掩模材料的组成和/或性质。 以这样的方式选择蚀刻速率,使得掩模在蚀刻步骤期间至少部分地溶解。 因此,可以容易地从半导体材料中去除掩模,并且在制造半导体部件期间就地施加附加层。

    Using a critical composition grading technique to deposit InGaAs epitaxial layers on InP substrates
    39.
    发明授权
    Using a critical composition grading technique to deposit InGaAs epitaxial layers on InP substrates 失效
    使用关键的组成分级技术在InP衬底上沉积InGaAs外延层

    公开(公告)号:US06482672B1

    公开(公告)日:2002-11-19

    申请号:US09186587

    申请日:1998-11-05

    IPC分类号: H01L2120

    摘要: A method for growing InxGa1−xAs epitaxial layer on a lattice mismatched InP substrate calls for depositing by organo-metallic vapor phase epitaxy, or other epitaxial layer growth technique, a plurality of discreet layers of InAsyP1−y over an InP substrate. These layers provide a buffer. Each succeeding buffer layer has a distinct composition which produces less than a critical amount of lattice mismatch relative to the preceding layer. An InxGa1−xAs epitaxial layer is grown over the buffer wherein 0.53≦x≦0.76. A resulting InGaAs structure comprises an InP substrate with at least one InAsP buffer layer sandwiched between the substrate and the InGaAs epitaxial layer. The buffer layer has a critical lattice mismatch of less than 1.3% relative to the substrate. Additional buffer layers will likewise have a lattice mismatch of no more than 1.3% relative to the preceding layer. The number of buffer layers is determined by the resulting bandgap desired in the InGaAs epitaxial layer, which, in turn, determines the composition of the InxGa1−xAs epitaxial layer, and thus, the lattice mismatch.

    摘要翻译: 在晶格失配的InP衬底上生长In x Ga 1-x As外延层的方法要求通过有机金属气相外延或其它外延层生长技术在InP衬底上沉积多个离散的InAsyP1-y层。 这些层提供了一个缓冲区。 每个后续缓冲层具有相对于前一层产生小于临界量的晶格失配的不同组成。 In x Ga 1-x As外延层生长在缓冲器上,其中0.53≤x≤0.76。所得的InGaAs结构包括InP衬底,其具有夹在衬底和InGaAs外延层之间的至少一个InAsP缓冲层。 缓冲层相对于衬底具有小于1.3%的临界晶格失配。 附加的缓冲层同样具有相对于前一层不超过1.3%的晶格失配。 缓冲层的数量由InGaAs外延层中所需的所得到的带隙确定,InGaAs外延层决定了In x Ga 1-x As外延层的组成,从而确定晶格失配。

    Method for producing a high-luminance semiconductor light-emitting device capable of operating at a low voltage
    40.
    发明授权
    Method for producing a high-luminance semiconductor light-emitting device capable of operating at a low voltage 有权
    一种能够以低电压工作的高亮度半导体发光装置的制造方法

    公开(公告)号:US06468818B2

    公开(公告)日:2002-10-22

    申请号:US09490534

    申请日:2000-01-25

    IPC分类号: H01L2100

    摘要: A semiconductor light-emitting device has a light-emitting section comprised of at least a lower clad layer, an active layer and an upper clad layer which are formed on a compound semiconductor substrate and a layer grown on the upper clad layer of the light-emitting section. When growing the current diffusion layer from a crystal interface on the upper clad layer in a lattice mismatching state in which the absolute value of a lattice matching factor &Dgr;a/a is not lower than 0.25% with respect to the upper clad layer at a crystal interface where the crystal composition changes on the upper clad layer of the light-emitting section, the growth rate at least at the start time of growth is made to be 1.0 &mgr;m/h or less.

    摘要翻译: 半导体发光器件具有至少包含形成在化合物半导体衬底上的下覆盖层,有源层和上覆盖层的发光部分和在发光元件的上覆盖层上生长的层, 发射部分。 当晶格匹配因子DELTAa / a的绝对值相对于晶体界面处的上包层不低于0.25%的晶格失配状态从上覆盖层上的晶体界面生长电流扩散层时 其中晶体组成在发光部分的上包覆层上变化,至少在生长开始时的生长速率为1.0mum / h以下。