公开(公告)号：US07180109B2

公开(公告)日：2007-02-20

申请号：US10922317

申请日：2004-08-18

申请人： Robert S. Chau ,  Doulgas Barlage ,  Been-Yih Jin

发明人： Robert S. Chau ,  Doulgas Barlage ,  Been-Yih Jin

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4908 ,  H01L29/458 ,  H01L29/66643 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S438/936

摘要： The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

摘要翻译： 本发明是一种新颖的场效应晶体管，其具有由形成在绝缘基板上的窄带隙半导体膜形成的沟道区。 在窄带隙半导体膜上形成栅极电介质层。 然后在栅极电介质上形成栅电极。 由宽带隙半导体膜或金属形成的一对源极/漏极区域形成在栅电极的相对侧并且与低带隙半导体膜相邻。

公开(公告)号：US07176075B2

公开(公告)日：2007-02-13

申请号：US11031183

申请日：2005-01-06

申请人： Robert S. Chau ,  Doulgas Barlage ,  Been-Yih Jin

发明人： Robert S. Chau ,  Doulgas Barlage ,  Been-Yih Jin

IPC分类号： H01L21/338 ,  H01L31/0328

CPC分类号： H01L29/4908 ,  H01L29/458 ,  H01L29/66643 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S438/936

摘要： The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

公开(公告)号：US06825506B2

公开(公告)日：2004-11-30

申请号：US10306640

申请日：2002-11-27

申请人： Robert S. Chau ,  Doulgas Barlage ,  Been-Yih Jin

发明人： Robert S. Chau ,  Doulgas Barlage ,  Been-Yih Jin

IPC分类号： H01L31072

CPC分类号： H01L29/4908 ,  H01L29/458 ,  H01L29/66643 ,  H01L29/66742 ,  H01L29/7839 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S438/936

摘要： The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

摘要翻译： 本发明是一种新颖的场效应晶体管，其具有由形成在绝缘基板上的窄带隙半导体膜形成的沟道区。 在窄带隙半导体膜上形成栅极电介质层。 然后在栅极电介质上形成栅电极。 由宽带隙半导体膜或金属形成的一对源极/漏极区域形成在栅电极的相对侧并与低带隙半导体膜相邻。

公开(公告)号：US20110180851A1

公开(公告)日：2011-07-28

申请号：US13038190

申请日：2011-03-01

申请人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

发明人： Brian S. Doyle ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Justin K. Brask ,  Robert S. Chau

IPC分类号： H01L29/772

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.

摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。

公开(公告)号：US20110156005A1

公开(公告)日：2011-06-30

申请号：US12655468

申请日：2009-12-30

申请人： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

发明人： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/772

CPC分类号： H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

摘要： A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

摘要翻译： 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US20100219396A1

公开(公告)日：2010-09-02

申请号：US12715034

申请日：2010-03-01

申请人： Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Been-Yih Jin ,  Jack T. Kavalieros ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/161 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/7782 ,  H01L29/78

摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.

摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。

公开(公告)号：US20100200917A1

公开(公告)日：2010-08-12

申请号：US12767681

申请日：2010-04-26

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

公开(公告)号：US20080237636A1

公开(公告)日：2008-10-02

申请号：US11729564

申请日：2007-03-29

申请人： Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

发明人： Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

IPC分类号： H01L29/778

CPC分类号： H01L29/1054 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7843 ,  H01L29/7851

摘要： A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

摘要翻译： 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。

公开(公告)号：US20080237575A1

公开(公告)日：2008-10-02

申请号：US11729565

申请日：2007-03-29

申请人： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/15 ,  H01L21/335

CPC分类号： H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

摘要翻译： 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

公开(公告)号：US06909151B2

公开(公告)日：2005-06-21

申请号：US10607632

申请日：2003-06-27

申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。