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公开(公告)号:US09674009B2
公开(公告)日:2017-06-06
申请号:US14942929
申请日:2015-11-16
Applicant: Rambus Inc.
Inventor: Yikui Jen Dong
CPC classification number: H04L25/03057 , H04B1/16 , H04B10/69 , H04B10/695 , H04L25/0272 , H04L25/0292
Abstract: An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.
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公开(公告)号:US09667359B2
公开(公告)日:2017-05-30
申请号:US14718019
申请日:2015-05-20
Applicant: Rambus Inc.
Inventor: Craig E. Hampel , Frederick A. Ware , Richard E. Perego
CPC classification number: H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
Abstract: A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
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公开(公告)号:US09653146B2
公开(公告)日:2017-05-16
申请号:US14869294
申请日:2015-09-29
Applicant: RAMBUS INC.
Inventor: Frederick A. Ware , Suresh Rajan , Scott C. Best
IPC: G06F3/00 , G11C11/408 , G11C5/04 , G11C11/4093 , G06F12/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076
CPC classification number: G11C11/4082 , G06F12/06 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/4093
Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
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公开(公告)号:US20170112376A1
公开(公告)日:2017-04-27
申请号:US15314404
申请日:2015-06-09
Applicant: Rambus Inc.
Inventor: Patrick R. Gill , David G. Stork
IPC: A61B3/113 , G02B5/18 , A61B3/14 , G06T3/40 , H04N5/33 , H04N7/18 , H04N5/225 , G02B27/42 , G06K9/00
CPC classification number: H04N5/33 , A61B3/113 , A61B3/14 , A61B3/145 , A61B3/152 , G02B5/1871 , G02B5/1876 , G02B27/4205 , G06K9/00604 , G06T3/4053 , H04N5/213 , H04N5/2253 , H04N5/2256 , H04N5/23241 , H04N5/23245 , H04N5/332 , H04N7/181 , H04N9/045 , H04N9/097 , H04N2209/048
Abstract: A sensing device with an odd-symmetry grating projects near-field spatial modulations onto an array of closely spaced pixels. Due to physical properties of the grating, the spatial modulations are in focus for a range of wavelengths and spacings. The spatial modulations are captured by the array, and photographs and other image information can be extracted from the resultant data. Pixels responsive to infrared light can be used to make thermal imaging devices and other types of thermal sensors. Some sensors are well adapted for tracking eye movements, and others for imaging barcodes and like binary images. In the latter case, the known binary property of the expected images can be used to simplify the process of extracting image data.
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公开(公告)号:US09632956B2
公开(公告)日:2017-04-25
申请号:US14874324
申请日:2015-10-02
Applicant: Rambus Inc.
Inventor: Ian Shaeffer , Arun Vaidyanath , Sanku Mukherjee
CPC classification number: G06F13/1678 , G06F1/3275 , G06F12/0246 , G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F13/4068 , G06F13/4072 , Y02D10/14 , Y02D10/151
Abstract: An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.
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公开(公告)号:US20170110188A1
公开(公告)日:2017-04-20
申请号:US15338872
申请日:2016-10-31
Applicant: Rambus Inc.
Inventor: Deepak Chandra Sekar , Gary Bela Bronner , Frederick A. Ware
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C13/0097 , G11C2213/15 , G11C2213/72 , G11C2213/74 , G11C2213/75 , G11C2213/78 , G11C2213/79
Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
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公开(公告)号:US20170103029A1
公开(公告)日:2017-04-13
申请号:US15284307
申请日:2016-10-03
Applicant: Rambus Inc.
Inventor: Frederick A. Ware , Kenneth L. Wright
CPC classification number: G06F13/1684 , G06F11/073 , G06F11/0772 , G06F13/4027 , Y02D10/14 , Y02D10/151
Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
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公开(公告)号:US20170099132A1
公开(公告)日:2017-04-06
申请号:US15209529
申请日:2016-07-13
Applicant: Rambus Inc.
Inventor: Hae-Chang Lee , Brian Leibowitz , Jaeha Kim , Jafar Savoj
CPC classification number: H04L7/0016 , G06Q10/06312 , G06Q10/103 , H04L7/0004 , H04L7/0062 , H04L7/033 , H04L7/0331 , H04L7/0334 , H04L25/062 , H04L2025/0349 , H04L2027/004 , H04L2027/0067 , H04L2027/0069
Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.
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公开(公告)号:US20170097905A1
公开(公告)日:2017-04-06
申请号:US15333001
申请日:2016-10-24
Applicant: Rambus Inc.
Inventor: Frederick A. Ware , Amir Amirkhany , Suresh Rajan , Mohammad Hekmat , Dinesh Patil
CPC classification number: G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号:US20170084046A1
公开(公告)日:2017-03-23
申请号:US15119701
申请日:2015-02-19
Applicant: Rambus Inc.
Inventor: Patrick R. Gill , David G. Stork , Patrick R. Johnstone
CPC classification number: G06T5/10 , G02B5/18 , G02B27/42 , G02B27/4205 , G02B27/46 , G06T7/246 , G06T2207/10004
Abstract: Computational diffractive imagers employ special optical phase gratings integrated with photodetector matrices. Such imagers do not require a lens, and so can be extremely small and inexpensive. Captured interference patterns are unintelligible to a human observer, but the captured data includes sufficient information to allow the image or aspects of the image to be computed. Computational diffractive imagers can be tailored to extract application-specific information or compute decisions (rather than compute an image) based on the optical signal. Both the phase grating and the signal processing can be optimized for the information in the visual field and the task at hand. For example, sequences of interference patterns can be compared to measure changes in angular position, and this information can be used to sense and measure motion. Such interference patterns can also be used for pattern recognition, such as to perform automated face detection and recognition.
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