公开(公告)号：US20240312535A1

公开(公告)日：2024-09-19

申请号：US18602974

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Paolo Tessariol

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10

Abstract: Control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.

公开(公告)号：US20240312521A1

公开(公告)日：2024-09-19

申请号：US18593671

申请日：2024-03-01

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Stephen W. Russell ,  Lorenzo Fratin

IPC: G11C16/04 ,  H10B43/10 ,  H10B43/20

CPC classification number: G11C16/0483 ,  H10B43/10 ,  H10B43/20

Abstract: Methods, systems, and devices for trench and multiple pier architecture for three-dimensional memory arrays are described. Manufacturing operations for a memory device may include forming trenches, and subsequently forming multiple types of pier structures extending between the trenches in a first horizontal direction, in a second horizontal direction or both. For example, the trenches may be arranged in a grid-like structure extending in one or more rows and one or more columns. A set of a first type of pier may be formed along each of the trenches, a set of a second type of pier may be formed between adjacent trenches in the first horizontal direction, and a set of a third type of pier may be formed between adjacent trenches in the second horizontal direction.

公开(公告)号：US20240312518A1

公开(公告)日：2024-09-19

申请号：US18586149

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Hari Giduturi ,  Fabio Pellizzer

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/409 ,  G11C29/50

CPC classification number: G11C11/5642 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/5628 ,  G11C29/50004

Abstract: Methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. Memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. A memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. The read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.

公开(公告)号：US20240312512A1

公开(公告)日：2024-09-19

申请号：US18674284

申请日：2024-05-24

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Randall J. Rooney

IPC: G11C11/4078 ,  G06F13/16 ,  G06F21/55

CPC classification number: G11C11/4078 ,  G06F13/1605 ,  G06F13/1668 ,  G06F21/554 ,  G06F2221/034

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. In one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.

公开(公告)号：US20240312498A1

公开(公告)日：2024-09-19

申请号：US18674788

申请日：2024-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mieko Kojima ,  Kazuyuki Morishige ,  Tetsuya Arai ,  Guangcan Chen

IPC: G11C7/10 ,  G11C5/06 ,  H03K19/017

CPC classification number: G11C7/1057 ,  G11C5/06 ,  G11C7/1039 ,  H03K19/01721

Abstract: Some embodiments provide an apparatus including a semiconductor substrate having source regions and regions alternately arranged in a first direction; gate electrodes between the source regions and the drain regions; a first wiring layer including first conductive patterns covering the source regions and second conductive patterns covering the drain regions; first via conductors between the first conductive patterns and the source regions; second via conductors between the second conductive patterns and the drain regions; a second wiring layer over the first wiring layer, including third conductive patterns covering the first conductive patterns and fourth conductive patterns covering the second conductive patterns; third via conductors between the third conductive patterns and the first conductive patterns; and fourth via conductors between the fourth conductive patterns and the second conductive patterns. The fourth via conductors are shifted from the third via conductors in a second direction perpendicular to the first direction.

公开(公告)号：US20240312494A1

公开(公告)日：2024-09-19

申请号：US18675997

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Shuai Xu ,  Michele Piccardi ,  Arvind Muralidharan ,  June Lee ,  Qisong Lin ,  Scott A. Stoller ,  Jun Shen

IPC: G11C5/14

CPC classification number: G11C5/144 ,  G11C5/147 ,  G11C5/148

Abstract: In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

公开(公告)号：US20240311311A1

公开(公告)日：2024-09-19

申请号：US18672640

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/1027 ,  G06F12/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G06F12/1027 ,  G06F12/0692 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G06F2212/68 ,  G11C16/0483

Abstract: A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.

公开(公告)号：US20240311299A1

公开(公告)日：2024-09-19

申请号：US18672310

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Xing Wang

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: A system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache. The processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. Detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. The processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.

公开(公告)号：US20240311288A1

公开(公告)日：2024-09-19

申请号：US18591692

申请日：2024-02-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle Brock-Petersen ,  Scheheresade Virani ,  Steven Gaskill

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Described are systems and methods for internal log management in memory sub-systems. An example memory sub-system comprises a controller managing one or more memory devices. The controller is configured to perform operations, comprising: maintaining a write pointer referencing a next data item position within a log buffer residing on a memory device of the one or more memory devices; maintaining a log retrieval pointer referencing a data retrieval position within the log buffer; storing, at a log buffer position specified by the write pointer, a data item reflecting a state of the system; advancing the write pointer by a size of the data item; responsive to determining that the write pointer exceeds an end of the log buffer, wrapping the write pointer around the end of the log buffer; responsive to receiving, from a host, a log retrieval request, retrieving the log data starting from the position within the log buffer referenced by the log retrieval pointer; transmitting the retrieved log data to the host; advancing the log retrieval pointer by a size of the retrieved log data; responsive to determining that the log retrieval pointer exceeds the end of the log buffer, wrapping the log retrieval pointer around the end of the log buffer.

公开(公告)号：US12096626B2

公开(公告)日：2024-09-17

申请号：US18149318

申请日：2023-01-03

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/532 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H10B43/27

Abstract: A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.