公开(公告)号：US5604909A

公开(公告)日：1997-02-18

申请号：US168744

申请日：1993-12-15

Applicant: Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

Inventor： Chandra Joshi ,  Paul Rodman ,  Peter Hsu ,  Monica R. Nofal

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC classification number: G06F9/3885 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3844

Abstract: A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.

Abstract translation: 计算系统具有第一和第二指令存储电路，每个指令存储电路存储用于并行输出的N个指令。 耦合到第一指令存储电路的指令调度电路调度存储在第一指令存储电路中的L指令，其中L小于或等于N.一个指令加载电路，耦合到指令调度电路和第一和第二指令 指令存储电路，在从第一指令存储电路发出L指令之后并且从第一指令存储电路调度进一步的指令之前，将来自第二指令存储电路的L指令加载到第一指令存储电路中。 还提供了用于绕过第二指令存储电路的旁路电路。

公开(公告)号：US4069498A

公开(公告)日：1978-01-17

申请号：US738783

申请日：1976-11-03

Applicant: Kailash Chandra Joshi

Inventor： Kailash Chandra Joshi

IPC: H01L23/34 ,  H01L23/12 ,  H01L23/367 ,  H01L23/433 ,  H01L23/02 ,  H01L39/02

CPC classification number: H01L23/4338 ,  H01L23/3677 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16151 ,  H01L2924/16152

Abstract: Heat is removed from the silicon devices in an integrated circuit package by means of a stud which is slidably mounted in a cap enclosing the integrated circuit device. A low melt solder is used to join the stud to the cap and the same solder is also deposited on the stud tip, which will subsequently contact the integrated circuit device in the package. After the integrated circuit, substrate and cap are assembled and sealed, the assembly is heated to melt the low melt solder so that the stud slides down and makes contact with the integrated circuit device. A controlled pressure can be applied to the stud if sliding does not occur. Thereafter, the assembly is allowed to cool. Upon cooling, a submicron gap exists between the solder on the tip of the stud and the device providing electrical isolation, but not significantly degrading the thermal path between the device and the ambient atmosphere.

Abstract translation: 借助于可滑动地安装在封闭集成电路装置的盖中的螺柱将热量从集成电路封装中的硅器件中去除。 使用低熔点焊料将螺柱连接到盖上，并且相同的焊料也沉积在螺柱尖端上，其随后将与封装中的集成电路器件接触。 在集成电路，基板和盖被组装和密封之后，加热组件以熔化低熔点焊料，使得螺柱向下滑动并与集成电路器件接触。 如果不发生滑动，则可以对螺柱施加受控的压力。 此后，使组件冷却。 在冷却时，在螺柱的尖端上的焊料和提供电隔离的装置之间存在亚微米间隙，但不会显着降低装置与环境大气之间的热路径。

公开(公告)号：US08236245B2

公开(公告)日：2012-08-07

申请号：US11827335

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G01N3/00

CPC classification number: B01L3/5027 ,  B01L3/502707 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0654 ,  B01L2300/0819 ,  B01L2300/0877 ,  G01N2035/00158

Abstract: A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.

Abstract translation: 逐像素，可数字寻址，像素化，前体，流体测定，包括优选在玻璃或塑料衬底上形成的多个像素的有源矩阵微结构，其中每个像素利用低温TFT和Si技术形成 包括（a）至少一个非功能化的，可数字寻址的测定传感器，和（b）可操作地邻近该传感器设置数字寻址和激励的电磁场产生结构，其可选择性地激励以产生在 所述至少一个测定传感器，环境电磁场环境，其被构造为协助在所述至少一个测定传感器上占有功能化至少一个可显示对所选流体测定法的亲和性的可数字寻址的测定位点 材料。

公开(公告)号：US08232109B2

公开(公告)日：2012-07-31

申请号：US11888491

申请日：2007-07-31

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele ,  Andrei Gindilis

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele ,  Andrei Gindilis

IPC: G01N21/00

CPC classification number: C12Q1/6813 ,  Y10S436/805

Abstract: A method of performing a fluid-material assay employing a device including at least one active pixel having a sensor with an assay site functionalized for selected fluid-assay material. The method includes exposing the pixel's sensor assay site to such material, and in conjunction with such exposing, and employing the active nature of the pixel, remotely requesting from the pixel's sensor assay site an assay-result output report. The method further includes, in relation to the employing step, creating, relative to the sensor's assay site in the at least one pixel, a predetermined, pixel-specific electromagnetic field environment.

Abstract translation: 使用包括至少一个具有传感器的活性像素的装置进行流体材料测定的方法，所述传感器具有用于所选流体测定材料功能化的测定位点。 该方法包括将像素的传感器测定位点暴露于这种材料，并结合这样的曝光，并采用像素的主动特性，从像素的传感器测定位点远程请求测定结果输出报告。 该方法还包括关于采用步骤，相对于至少一个像素中的传感器的测定位置产生预定的像素特定的电磁场环境。

公开(公告)号：US08231831B2

公开(公告)日：2012-07-31

申请号：US11827174

申请日：2007-07-10

Applicant: John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

Inventor： John W. Hartzell ,  Pooran Chandra Joshi ,  Paul J. Schuele

IPC: G01N21/00

CPC classification number: B01L3/5027 ,  B01L3/502707 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0819 ,  B01L2300/0877 ,  B01L2300/1822 ,  B01L2300/1827

Abstract: A pixel-by-pixel digitally-addressable, pixelated, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one functionalized, digitally-addressable assay sensor including at least one functionalized, digitally-addressable assay site which has been affinity-functionalized to respond to a selected, specific fluid-assay material, and (b) disposed operatively adjacent that sensor and its associated assay site, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the sensor and its associated assay site, a selected, ambient, electromagnetic field environment which is structured to assist, selectively and optionally only, in the reading-out of an assay-result response from the assay sensor and assay site.

Abstract translation: 逐像素可数字寻址，像素化，流体测定，包括优选地形成在玻璃或塑料基板上的多个像素的有源矩阵微结构，其中利用低温TFT和Si技术形成的每个像素包括（ a）至少一个功能化的，可数字寻址的测定传感器，其包括至少一个官能化的，可数字寻址的测定位点，其已经被亲和功能化以响应所选择的特定流体测定材料，和（b）可操作地邻近该传感器 以及其相关联的测定位点，可数字寻址和可激励的电磁场创建结构，其可选择性地激励以在传感器及其相关联的测定位点附近产生所选择的环境电磁场环境，其被构造为有选择地辅助 并且可选地仅在从测定传感器和测定位点读出测定结果响应中。

公开(公告)号：US08133822B2

公开(公告)日：2012-03-13

申请号：US12197045

申请日：2008-08-22

Applicant: Jiandong Huang ,  Pooran Chandra Joshi ,  Hao Zhang ,  Apostolos T. Voutsas

Inventor： Jiandong Huang ,  Pooran Chandra Joshi ,  Hao Zhang ,  Apostolos T. Voutsas

IPC: H01L21/324

CPC classification number: C23C16/30 ,  C23C16/24 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/31608

Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.

Abstract translation: 提供了一种用于形成具有中间带隙过渡层的硅（Si）纳米晶体嵌入式Si氧化物电致发光（EL）器件的方法。 该方法提供高度掺杂的Si底部电极，并且形成覆盖电极的中带隙电绝缘膜。 在其中X小于2的中间带隙绝缘电介质膜上形成Si纳米晶体嵌入的SiOx膜层，并且透明顶部电极覆盖在Si纳米晶体嵌入的SiOx膜层上。 中间带隙电介质膜的带隙约为Si纳米晶体嵌入的SiOx膜的带隙的一半。 在一个方面，Si纳米晶体嵌入的SiO x膜具有约10电子伏特（eV）的带隙（Eg），并且中带隙绝缘电介质膜具有约5eV的带隙。 通过将高能隧道工艺分成两个较低能量的隧穿步骤，由于大功率热电子引起的潜在损害降低。

公开(公告)号：US08054540B2

公开(公告)日：2011-11-08

申请号：US12259986

申请日：2008-10-28

Applicant: Jiandong Huang ,  Pooran Chandra Joshi ,  Hao Zhang ,  Apostolos T. Voutsas

Inventor： Jiandong Huang ,  Pooran Chandra Joshi ,  Hao Zhang ,  Apostolos T. Voutsas

IPC: H01S5/00

CPC classification number: C23C16/30 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  G02B6/0229 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31608 ,  H01S3/0632 ,  H01S3/169

Abstract: A method is provided for optical amplification using a silicon (Si) nanocrystal embedded silicon oxide (SiOx) waveguide. The method provides a Si nanocrystal embedded SiOx waveguide, where x is less than 2, having a quantum efficiency of greater than 10%. An optical input signal is supplied to the Si nanocrystal embedded SiOx waveguide, having a first power at a first wavelength in the range of 700 to 950 nm. The Si nanocrystal embedded SiOx waveguide is pumped with an optical source having a second power at a second wavelength in a range of 250 to 550 nm. As a result, an optical output signal having a third power is generated, greater than the first power, at the first wavelength. In one aspect, the third power increases in response to the length of the waveguide strip.

Abstract translation: 提供了使用硅（Si）纳米晶体嵌入式氧化硅（SiO x）波导进行光放大的方法。 该方法提供了Si纳米晶体内置的SiOx波导，其中x小于2，量子效率大于10％。 将光输入信号提供给Si纳米晶体嵌入的SiO x波导，其具有在700至950nm范围内的第一波长的第一功率。 Si纳米晶体埋入的SiOx波导用具有第二波长的第二功率的光源在250至550nm的范围内泵浦。 结果，在第一波长处产生具有大于第一功率的第三功率的光输出信号。 在一个方面，第三功率响应于波导条的长度而增加。

公开(公告)号：US08000571B2

公开(公告)日：2011-08-16

申请号：US12432209

申请日：2009-04-29

Applicant: Jiandong Huang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

Inventor： Jiandong Huang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

IPC: G02B6/34

CPC classification number: H05B33/26 ,  H05B33/22

Abstract: Light emitting and waveguide devices with single-sided photonic bandgaps are provided. The light emitting device is formed from a heavily doped silicon (Si) bottom electrode, and a Si-containing dielectric layer embedded Si nanoparticles overlying the bottom electrode. A transparent indium tin oxide (ITO) top electrode overlies the Si-containing dielectric layer, and a photonic bandgap (PBG) Bragg reflector underlies the Si bottom electrode. The PBG Bragg reflector includes at least one periodic bi-layer of films with different refractive indexes. The single-sided photonic bandgap planar waveguide interface is formed from a planar waveguide and a PBG Bragg reflector underlying the planar waveguide.

Abstract translation: 提供具有单面光子带隙的发光和波导器件。 发光器件由重掺杂的硅（Si）底部电极形成，并且含有Si的电介质层嵌入覆盖在底部电极上的Si纳米颗粒。 透明氧化铟锡（ITO）顶部电极覆盖含Si介电层，光子带隙（PBG）布拉格反射器位于Si底部电极的正下方。 PBG布拉格反射器包括具有不同折射率的膜的至少一个周期性双层膜。 单面光子带隙平面波导接口由平面波导和平面波导下面的PBG布拉格反射器形成。

公开(公告)号：US20100278475A1

公开(公告)日：2010-11-04

申请号：US12432209

申请日：2009-04-29

Applicant: Jiandong Huang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

Inventor： Jiandong Huang ,  Pooran Chandra Joshi ,  Apostolos T. Voutsas

IPC: G02F1/295 ,  H01L33/00

CPC classification number: H05B33/26 ,  H05B33/22

Abstract: Light emitting and waveguide devices with single-sided photonic bandgaps are provided. The light emitting device is formed from a heavily doped silicon (Si) bottom electrode, and a Si-containing dielectric layer embedded Si nanoparticles overlying the bottom electrode. A transparent indium tin oxide (ITO) top electrode overlies the Si-containing dielectric layer, and a photonic bandgap (PBG) Bragg reflector underlies the Si bottom electrode. The PBG Bragg reflector includes at least one periodic bi-layer of films with different refractive indexes. The single-sided photonic bandgap planar waveguide interface is formed from a planar waveguide and a PBG Bragg reflector underlying the planar waveguide.

Abstract translation: 提供具有单面光子带隙的发光和波导器件。 发光器件由重掺杂的硅（Si）底部电极形成，并且含有Si的电介质层嵌入覆盖在底部电极上的Si纳米颗粒。 透明氧化铟锡（ITO）顶部电极覆盖含Si介电层，光子带隙（PBG）布拉格反射器位于Si底部电极的正下方。 PBG布拉格反射器包括具有不同折射率的膜的至少一个周期性双层膜。 单面光子带隙平面波导接口由平面波导和平面波导下面的PBG布拉格反射器形成。

公开(公告)号：US07723242B2

公开(公告)日：2010-05-25

申请号：US11327612

申请日：2006-01-06

Applicant: Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

Inventor： Pooran Chandra Joshi ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC: H01L21/469

CPC classification number: H01L21/31608 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/3105 ,  H01L21/31662

Abstract: A method is provided for additionally oxidizing a thin-film oxide. The method includes: providing a substrate; depositing an MyOx (M oxide) layer overlying the substrate, where M is a solid element having an oxidation state in a range of +2 to +5; treating the MyOx layer to a high density plasma (HDP) source; and, forming an MyOk layer in response to the HDP source, where k>x. In one aspect, the method further includes decreasing the concentration of oxide charge in response to forming the MyOk layer. In another aspect, the MyOx layer is deposited with an impurity N, and the method further includes creating volatile N oxides in response to forming the MyOk layer. For example, the impurity N may be carbon and the method creates a volatile carbon oxide.

Abstract translation: 提供了另外氧化薄膜氧化物的方法。 该方法包括：提供衬底; 沉积覆盖衬底的MyOx（M氧化物）层，其中M是具有+2至+5范围内的氧化态的固体元素; 将MyOx层处理成高密度等离子体（HDP）源; 并且响应于HDP源形成MyOk层，其中k> x。 在一个方面，该方法还包括响应于形成MyOk层而降低氧化物电荷的浓度。 在另一方面，MyOx层沉积有杂质N，并且该方法还包括响应于形成MyOk层而产生挥发性N氧化物。 例如，杂质N可以是碳，并且该方法产生挥发性碳氧化物。