公开(公告)号：US07453159B2

公开(公告)日：2008-11-18

申请号：US11616857

申请日：2006-12-27

Applicant: Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

Inventor： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L23/525 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract translation: 半导体芯片包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体基板。 在半导体衬底上形成接合焊盘布线图形。 焊盘重排图案电连接到接合焊盘布线图案。 垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。 因此，利用本发明的实施例，由此可以大大减小总体芯片尺寸，并且可以制造MCP而没有上述问题。

公开(公告)号：US20080261366A1

公开(公告)日：2008-10-23

申请号：US12125280

申请日：2008-05-22

Applicant: Sang-hun JEON ,  Chung-woo Kim

Inventor： Sang-hun JEON ,  Chung-woo Kim

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device having an improved erase efficiency and a method of manufacturing the same are provided. The method includes: forming a stack structure of a tunnel dielectric layer, a charge trapping layer, a charge blocking layer and a gate on a semiconductor substrate; and performing a post treatment of the gate using an oxygen or CF4 plasma or ion implantation to increase a work function of an element forming the gate. Since the work function of the metal layer forming the gate can be further increased, an electron back tunneling can be suppressed during an erase operation.

Abstract translation: 提供了具有改进的擦除效率的非易失性存储器件及其制造方法。 该方法包括：在半导体衬底上形成隧道介电层，电荷俘获层，电荷阻挡层和栅极的堆叠结构; 以及使用氧或CF 4等离子体或离子注入来执行栅极的后处理以增加形成栅极的元件的功函数。 由于可以进一步增加形成栅极的金属层的功函数，所以可以在擦除操作期间抑制电子反向隧穿。

公开(公告)号：US20080225501A1

公开(公告)日：2008-09-18

申请号：US12076274

申请日：2008-03-14

Applicant: Chung-Woo Cho ,  Chang-Sup Ryu ,  Soon-Jin Cho ,  Seung-Chul Kim

Inventor： Chung-Woo Cho ,  Chang-Sup Ryu ,  Soon-Jin Cho ,  Seung-Chul Kim

IPC: H05K7/10 ,  H01K3/10

CPC classification number: H05K3/421 ,  H05K3/108 ,  H05K3/423 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49165

Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The printed circuit board, which includes a first insulation layer, a first via that penetrates the first insulation layer, and a first pad formed on one surface of the first insulation layer, where a whole of or a portion of the first pad is buried in the first via, has a portion of or the whole of the pad buried in the via, so that the contact area between the pad and the via may be increased, and the printed circuit board can be given greater reliability.

Abstract translation: 公开了印刷电路板及其制造方法。 印刷电路板包括第一绝缘层，穿过第一绝缘层的第一通孔和形成在第一绝缘层的一个表面上的第一焊盘，其中第一焊盘的整体或一部分被埋在 第一通孔具有埋在通孔中的焊盘的一部分或全部，从而可以增加焊盘和通孔之间的接触面积，并且可以赋予印刷电路板更高的可靠性。

公开(公告)号：US20080212376A1

公开(公告)日：2008-09-04

申请号：US12025372

申请日：2008-02-04

Applicant: Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

Inventor： Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

IPC: G11C16/06 ,  H01L21/336 ,  G11C7/00

CPC classification number: G11C11/5621 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551

Abstract: Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

Abstract translation: 提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。 互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。 第一和第二非易失性存储器被布置成使得其上表面相邻。

公开(公告)号：US20080157186A1

公开(公告)日：2008-07-03

申请号：US11980352

申请日：2007-10-31

Applicant: Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

Inventor： Wan-jun Park ,  Jo-won Lee ,  Sang-hun Jeon ,  Chung-woo Kim

IPC: H01L29/792

CPC classification number: H01L21/28273 ,  H01L21/28282

Abstract: A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.

Abstract translation: 提供了包括金属 - 绝缘体转变（MIT）材料的非易失性存储器件。 非易失性存储器件包括具有隧道层，电荷陷阱层，形成在衬底上的阻挡层和栅电极的栅极堆叠，其中隧道层和阻挡层中的至少一个由MIT形成 金属 - 绝缘体转变）材料。

公开(公告)号：US07327758B2

公开(公告)日：2008-02-05

申请号：US10023958

申请日：2001-12-17

Applicant: Addepalli Sateesh Kumar ,  Chandrasekaran Nageswara Gupta ,  Tushar Ramanlal Shah ,  Debaditya Mukherjee ,  Thomas Yat Chung Woo ,  Khalid Seikh ,  Jai Prakash Agrawal

Inventor： Addepalli Sateesh Kumar ,  Chandrasekaran Nageswara Gupta ,  Tushar Ramanlal Shah ,  Debaditya Mukherjee ,  Thomas Yat Chung Woo ,  Khalid Seikh ,  Jai Prakash Agrawal

IPC: H04L5/22 ,  H04J3/04

CPC classification number: H04W28/20 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0026 ,  H04L12/6402 ,  H04L12/6418 ,  H04Q11/0005 ,  H04Q11/0066 ,  H04Q11/0071 ,  H04Q2011/0033

Abstract: To better utilize the variable bandwidth of wireless links, a network node in accordance with the present invention escapes rigid bandwidth hierarchy of conventional TDM protocols, which is not suited for fully using the available bandwidth of a wireless link. Specifically, many embodiments of the present invention use TDM frames that have payloads, which do not strictly conform to the bandwidth hierarchy of conventional TDM protocols. For example, many embodiments of the present invention form TDM frames having a payload that is a non-integer multiple of a base bandwidth, such as OC-1/STS-1.

Abstract translation: 为了更好地利用无线链路的可变带宽，根据本发明的网络节点逃避常规TDM协议的刚性带宽层级，其不适合于完全使用无线链路的可用带宽。 具体地，本发明的许多实施例使用具有有效载荷的TDM帧，其不严格地符合常规TDM协议的带宽层级。 例如，本发明的许多实施例形成具有作为基本带宽的非整数倍的有效载荷的TDM帧，例如OC-1 / STS-1。

公开(公告)号：US20070275567A1

公开(公告)日：2007-11-29

申请号：US11217483

申请日：2005-09-02

Applicant: Chunhua Xu ,  San-Qiang Shi ,  Yang Liu ,  Chung Woo

Inventor： Chunhua Xu ,  San-Qiang Shi ,  Yang Liu ,  Chung Woo

IPC: H01L21/31

CPC classification number: C01G1/02 ,  B22F2998/00 ,  B82Y30/00 ,  C01P2004/16 ,  C30B29/16 ,  C30B29/60 ,  D01F9/08 ,  Y10S977/762 ,  Y10S977/811 ,  B22F1/0025 ,  B22F1/0088

Abstract: Metal oxide nanowires are being investigated to make nanodevices and nanosensors. High operation temperatures or vacuum is required in the manufacturing of metal oxide nanowires by existing vapour phase evaporation methods. This invention provides a method of manufacturing metal oxide nanowires by first providing a metal to form a non-linear substantially planar structure defining a surface. The metal is then heated and maintained at a temperature from 300 to 800° C., and then exposed to oxygen and water vapour containing air stream for a sufficient period of time to form the metal oxide nanowires. The oxygen containing air stream flows in a direction substantially parallel to the plane of the structure. Relatively low temperatures may be used and no vacuum is required in this method, thereby reducing the overall manufacturing costs. Further, this method is able to manufacture different densities of the metal oxide nanowires simultaneously.

Abstract translation: 正在研究金属氧化物纳米线以制备纳米器件和纳米传感器。 通过现有的气相蒸发方法在金属氧化物纳米线的制造中需要高的操作温度或真空度。 本发明提供一种通过首先提供金属以形成限定表面的非线性基本平面结构来制造金属氧化物纳米线的方法。 然后将金属加热并保持在300至800℃的温度，然后暴露于含氧气和水蒸汽的空气流中足够的时间以形成金属氧化物纳米线。 含氧空气流在基本平行于结构平面的方向上流动。 可以使用相对低的温度，并且在该方法中不需要真空，从而降低整体制造成本。 此外，该方法能够同时制造不同密度的金属氧化物纳米线。

公开(公告)号：US07263091B1

公开(公告)日：2007-08-28

申请号：US10156720

申请日：2002-05-23

Applicant: Hsien-Chung Woo ,  Dennis C. Ferguson ,  Scott Mackie ,  Manoj Leelanivas

Inventor： Hsien-Chung Woo ,  Dennis C. Ferguson ,  Scott Mackie ,  Manoj Leelanivas

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L45/60 ,  H04L49/354 ,  H04L49/45 ,  H04L49/552

Abstract: A routing system decouples the routing functionality from the packet forwarding functionality. The decoupling of functionality is accomplished by coupling a set of routing engines to a set of packet-forwarding engines via a switch. The decoupling of functionality allows the routing system to easily be reconfigured and scaled. The decoupling of functionality also reduces the susceptibility of concurrently executing software processes from the malfunction of a single software process.

Abstract translation: 路由系统将路由功能与数据包转发功能分离。 通过将一组路由引擎经由交换机耦合到一组分组转发引擎来实现功能的解耦。 功能的解耦允许路由系统轻松重新配置和缩放。 功能的解耦也降低了从单个软件过程的故障同时执行软件过程的敏感性。

公开(公告)号：US20070185337A1

公开(公告)日：2007-08-09

申请号：US11596580

申请日：2005-05-25

Applicant: Seong-Jin Kim ,  Chung-woo Lim ,  Chang Boo ,  Jung-hoon Oh ,  Ki Kim ,  Jae Lee ,  Duk Won

Inventor： Seong-Jin Kim ,  Chung-woo Lim ,  Chang Boo ,  Jung-hoon Oh ,  Ki Kim ,  Jae Lee ,  Duk Won

IPC: C07D207/04

CPC classification number: C07D207/273

Abstract: A process for the preparation of chiral 4-hydroxy-2-oxo-1-pyrrolidine acetamide includes adding sodium cyanide together with citric acid to a solution of chiral epichlorohydrin to obtain chiral 3-chloro-2-hydroxypropionitrile by ring opening reaction of the chiral epichlorohydrin, reacting the obtained product with an alcohol containing hydrochloride gas to obtain chiral 4-chloro-3-hydroxybutyric acid ester, and reacting the obtained product in a presence of a base with glycinamide or with glycine ester accompanied by ammonolysis with ammonia to produce the targeted chiral 4-hydroxy-2-oxo-1-pyrrolidine acetamide.

Abstract translation: 手性4-羟基-2-氧代-1-吡咯烷乙酰胺的制备方法包括将氰化钠与柠檬酸一起加入到手性表氯醇的溶液中，以通过手性的开环反应获得手性3-氯-2-羟基丙腈 将得到的产物与含有盐酸气体的醇反应，得到手性4-氯-3-羟基丁酸酯，并使得到的产物在碱的存在下与甘氨酰胺或甘氨酸酯反应，伴随着氨的氨解，生成 靶向手性4-羟基-2-氧代-1-吡咯烷乙酰胺。

公开(公告)号：US07202521B2

公开(公告)日：2007-04-10

申请号：US10961481

申请日：2004-10-12

Applicant: Moon-kyung Kim ,  Chung-woo Kim ,  Jo-won Lee ,  Eun-hong Lee ,  Hee-soon Chae

Inventor： Moon-kyung Kim ,  Chung-woo Kim ,  Jo-won Lee ,  Eun-hong Lee ,  Hee-soon Chae

IPC: H01L29/76

CPC classification number: G11C16/0475 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on the semiconductor layer, the upper stack structure and the semiconductor layer forming an upper SONOS memory device, and a lower stack structure formed under the semiconductor layer, the lower stack structure and the semiconductor layer forming a lower SONOS memory device.

Abstract translation: 在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）存储器件及其制造和操作方法中，SONOS存储器件包括包括源极和漏极区域以及沟道区域的半导体层，上部堆叠结构形成在 半导体层，上层堆叠结构和形成上SONOS存储器件的半导体层，以及形成在半导体层下的下堆叠结构，下堆叠结构和半导体层形成下SONOS存储器件。