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公开(公告)号：US20200221492A1
公开(公告)日：2020-07-09
申请号：US16751340
申请日：2020-01-24
Abstract: In one embodiment, a method is performed by a wireless station. The method includes determining that a wireless network provides relay service. The wireless network includes an access point and one or more relay nodes. The method further includes transmitting a relay-service desirability indication to the access point. The method also includes receiving a relay-service confirmation from the access point. The wireless station is operable to transmit at a first station-transmission power level during a first time period and a second station-transmission power level during a second time period. The second station-transmission power level is a reduced station-transmission power level as compared to the first station-transmission power level. In addition, the method includes transmitting an uplink transmission at the second station-transmission power level responsive to the relay-service confirmation from the access point.
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42.发明申请公开(公告)号：US20200020401A1
公开(公告)日：2020-01-16
申请号：US16580099
申请日：2019-09-24
Inventor： Hyoung Seub RHIE
Abstract: A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.
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公开(公告)号：US10303370B2
公开(公告)日：2019-05-28
申请号：US15976255
申请日：2018-05-10
Inventor： Jin-Ki Kim
Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
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公开(公告)号：US10140028B2
公开(公告)日：2018-11-27
申请号：US15957120
申请日：2018-04-19
Inventor： Peter B. Gillingham , Graham Allan
IPC: G11C8/00 , G06F3/06 , G11C7/22 , G11C7/10 , G11C14/00 , G06F13/16 , G11C16/04 , G11C16/32 , G11C16/28 , G11C16/10 , H03K5/00
Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
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公开(公告)号：US20180331620A1
公开(公告)日：2018-11-15
申请号：US15892587
申请日：2018-02-09
Inventor： Peter Vlasenko , Huy Tuong Mai
CPC classification number: H02M3/07 , G05F1/625 , G05F3/02 , H02M1/34 , H02M3/073 , H03K5/086 , H03L7/0895
Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
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Patent Agency Ranking
公开(公告)号：US20180314424A1
公开(公告)日：2018-11-01
申请号：US15957120
申请日：2018-04-19
Inventor： Peter B. GILLINGHAM , Graham ALLAN
IPC: G06F3/06 , G11C7/22 , G11C16/32 , G11C16/28 , G11C16/10 , G11C16/04 , G11C14/00 , G11C7/10 , G06F13/16 , H03K5/00
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
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公开(公告)号：US09996274B2
公开(公告)日：2018-06-12
申请号：US15419246
申请日：2017-01-30
Inventor： Jin-Ki Kim
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0679 , G06F12/0246 , G06F2212/7201
Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
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公开(公告)号：US09986585B2
公开(公告)日：2018-05-29
申请号：US14813154
申请日：2015-07-30
CPC classification number: H04W74/004 , H04B7/15507 , H04W74/0816
Abstract: In one embodiment, a method is performed by a wireless station. The method includes determining that a wireless network provides relay service. The wireless network includes an access point and one or more relay nodes. The method further includes transmitting a relay-service desirability indication to the access point. The method also includes receiving a relay-service confirmation from the access point. The wireless station is operable to transmit at a first station-transmission power level during a first time period and a second station-transmission power level during a second time period. The second station-transmission power level is a reduced station-transmission power level as compared to the first station-transmission power level. In addition, the method includes transmitting an uplink transmission at the second station-transmission power level responsive to the relay-service confirmation from the access point.
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公开(公告)号：US09836391B2
公开(公告)日：2017-12-05
申请号：US14457567
申请日：2014-08-12
Inventor： Hong Beom Pyeon , Jin-Ki Kim , HakJune Oh
IPC: G06F12/02 , G06F12/0893 , G11C7/10
CPC classification number: G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
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公开(公告)号：US20170185297A1
公开(公告)日：2017-06-29
申请号：US15400432
申请日：2017-01-06
Inventor： Jin-Ki KIM
CPC classification number: G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
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