公开(公告)号：US10303370B2

公开(公告)日：2019-05-28

申请号：US15976255

申请日：2018-05-10

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

公开(公告)号：US09996274B2

公开(公告)日：2018-06-12

申请号：US15419246

申请日：2017-01-30

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

公开(公告)号：US09836391B2

公开(公告)日：2017-12-05

申请号：US14457567

申请日：2014-08-12

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC: G06F12/02 ,  G06F12/0893 ,  G11C7/10

CPC classification number: G06F12/0246 ,  G06F12/0893 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/7203 ,  G06F2212/7208 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087 ,  G11C2207/2245

Abstract: Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

公开(公告)号：US09281047B2

公开(公告)日：2016-03-08

申请号：US14265852

申请日：2014-04-30

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki Kim ,  HakJune Oh

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

公开(公告)号：US11049574B2

公开(公告)日：2021-06-29

申请号：US16886977

申请日：2020-05-29

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim ,  Peter B. Gillingham

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US09779804B2

公开(公告)日：2017-10-03

申请号：US15345552

申请日：2016-11-08

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09490014B2

公开(公告)日：2016-11-08

申请号：US14964958

申请日：2015-12-10

Applicant: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C16/00 ,  G11C16/08 ,  G06F13/42 ,  G11C5/06 ,  G11C7/10 ,  G11C8/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US08964440B2

公开(公告)日：2015-02-24

申请号：US14082454

申请日：2013-11-18

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim

IPC: G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  H01L25/065 ,  H01L21/50 ,  H01L25/18

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  H01L21/50 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).

Abstract translation: 公开了一种包括非易失性存储器件的堆叠。 堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

公开(公告)号：US11150808B2

公开(公告)日：2021-10-19

申请号：US16891402

申请日：2020-06-03

Applicant: Conversant Intellectual Property Management Inc.

Inventor： Jin-Ki Kim

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

公开(公告)号：US11017849B2

公开(公告)日：2021-05-25

申请号：US16866818

申请日：2020-05-05

Applicant: Conversant Intellectual Property Management Inc.

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16 ,  G11C16/34 ,  G06F1/12 ,  G11C16/06

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.