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123 条记录 (耗时 0.029 秒)

    Optical alignment method and apparatus
    42.
    发明授权
    Optical alignment method and apparatus 失效
    光学对准方法和装置

    公开(公告)号：US07443505B2

    公开(公告)日：2008-10-28

    申请号：US11635578

    申请日：2006-12-08

    申请人： Jong Jin Lee ,  Hyun Seo Kang

    发明人： Jong Jin Lee ,  Hyun Seo Kang

    IPC分类号： G01B11/00 ,  G01B11/26 ,  G01N21/86 ,  G01V8/00 ,  G02B6/26 ,  G02B6/42

    CPC分类号： G02B6/4227 ,  G02B6/4204

    摘要： In disclosed optical alignment method and apparatus thereof, external reflection entering laser diode by feedback from transmission line of low cost bidirectional optical transceiver module without optical isolator for subscribers is reduced so as to reduce RIN considering high optical coupling efficiency. The external reflection is minimized using property that output current increases in proportion to external reflection during optical alignment. For optimal optical alignment, external reflection and RIN are previously measured according to optical alignment position between subassembly and optical fiber. Optimal position is determined by both light output and RIN, and predetermined ratio of the mPD output current of minimum RIN position to that of maximum light output power position.

    摘要翻译： 在所公开的光学对准方法及其装置中，减少了由不具有用户用光隔离器的低成本双向光收发器模块的传输线反馈进入激光二极管的外部反射，以便考虑到高的光耦合效率来降低RIN。 使用在光学对准期间输出电流与外部反射成比例地增加的性质来最小化外部反射。 为了最佳的光学对准，预先根据子组件和光纤之间的光学对准位置来测量外部反射和RIN。 最佳位置由光输出和RIN两者确定，最小RIN位置的mPD输出电流与最大光输出功率位置的预定比例。

    METHODS OF FABRICATING CMOS IMAGE SENSORS
    43.
    发明申请
    METHODS OF FABRICATING CMOS IMAGE SENSORS 审中-公开
    制作CMOS图像传感器的方法

    公开(公告)号：US20080182354A1

    公开(公告)日：2008-07-31

    申请号：US11950249

    申请日：2007-12-04

    申请人： Jong-Jin Lee ,  Ju-Hyun Ko ,  Jong-Eun Park ,  Hyun-Suk Kim ,  Dong-Yoon Jang

    发明人： Jong-Jin Lee ,  Ju-Hyun Ko ,  Jong-Eun Park ,  Hyun-Suk Kim ,  Dong-Yoon Jang

    IPC分类号： H01L31/18

    CPC分类号： H01L27/14643 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14681 ,  H01L27/14689

    摘要： CMOS image sensors and related methods of fabricating CMOS image sensors are disclosed. Fabrication of a CMOS image sensor can include forming a first impurity region having a first conductivity type in a semiconductor substrate. A second impurity region having a second conductivity type is formed in the semiconductor substrate adjacent to the first impurity region. A third impurity region having the first conductivity type is formed in the semiconductor substrate and located below the second impurity region. A transfer gate is formed on the semiconductor substrate and at least partially overlaps the first, second, and third impurity regions. A photo sensitive device is formed in the semiconductor substrate and adjacent to one side of the transfer gate. A floating diffusion region is formed in the semiconductor substrate and located adjacent to an opposite side of the transfer gate from the photosensitive device.

    摘要翻译： 公开了CMOS图像传感器和制造CMOS图像传感器的相关方法。 CMOS图像传感器的制造可以包括在半导体衬底中形成具有第一导电类型的第一杂质区域。 在与第一杂质区相邻的半导体衬底中形成具有第二导电类型的第二杂质区。 具有第一导电类型的第三杂质区形成在半导体衬底中并位于第二杂质区的下方。 传输栅极形成在半导体衬底上并且至少部分地与第一，第二和第三杂质区重叠。 光敏元件形成在半导体衬底中并与传输门的一侧相邻。 浮动扩散区域形成在半导体衬底中并且位于与传感栅极的与光敏器件相反的一侧。

    Method of manufacturing copper-clad laminate for VOP application
    44.
    发明申请
    Method of manufacturing copper-clad laminate for VOP application 有权
    制造用于VOP应用的覆铜层压板的方法

    公开(公告)号：US20080073025A1

    公开(公告)日：2008-03-27

    申请号：US11524401

    申请日：2006-09-21

    申请人： Jong Jin Lee ,  Young Hwan Shin ,  Jae Min Choi ,  Chang Yul Oh

    发明人： Jong Jin Lee ,  Young Hwan Shin ,  Jae Min Choi ,  Chang Yul Oh

    IPC分类号： B32B37/00

    CPC分类号： B32B38/04 ,  B32B37/12 ,  B32B2038/047 ,  B32B2311/12 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/0097 ,  H05K3/025 ,  H05K3/421 ,  H05K2203/0152 ,  H05K2203/1388 ,  H05K2203/1536 ,  Y10T156/1052 ,  Y10T156/1082

    摘要： Disclosed herein is a method of manufacturing a copper-clad laminate for Via-On-Pad application. The pad includes the steps of providing a first copper foil layer and a second copper foil layer, on the first surfaces of which protective layers are formed; placing two sets of a first copper foil layer, an insulating layer and a second copper foil layer above and below an adhesive layer, respectively; removing the protective layers, which have been respectively formed on the second copper foil layers, and parts of the second copper foil layers; forming via holes by removing parts of the insulating layers through the regions from which the parts of the second copper foil layers have been removed, using laser processing; and forming two copper-clad laminates by removing the protective layers, which have been respectively formed on one surface of one first copper foil layer and one surface of the other first copper foil layer, and the adhesive layer.

    摘要翻译： 本文公开了一种制造用于Via-On-Pad应用的覆铜层压板的方法。 该垫包括在形成有保护层的第一表面上提供第一铜箔层和第二铜箔层的步骤; 在粘合剂层上分别放置两组第一铜箔层，绝缘层和第二铜箔层; 去除分别形成在第二铜箔层上的保护层和第二铜箔层的部分; 通过使用激光加工从已除去了第二铜箔层的部分的区域去除绝缘层的一部分来形成通孔; 并且通过去除分别形成在一个第一铜箔层的一个表面和另一个第一铜箔层的一个表面上的保护层和粘合剂层来形成两个覆铜层压板。

    Manufacturing method package substrate
    45.
    发明申请
    Manufacturing method package substrate 审中-公开
    制造方法封装衬底

    公开(公告)号：US20070298546A1

    公开(公告)日：2007-12-27

    申请号：US11785093

    申请日：2007-04-13

    申请人： Jong-Jin Lee ,  Sun-Moon Kim ,  Mi-Seon Shin ,  Yong-Bin Lee

    发明人： Jong-Jin Lee ,  Sun-Moon Kim ,  Mi-Seon Shin ,  Yong-Bin Lee

    IPC分类号： H01L21/00 ,  H01L21/44

    CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/42 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/1581 ,  H01L2224/05599

    摘要： A manufacturing method of a package substrate is disclosed. The method for manufacturing a package substrate is by forming a bump on a bump pad in a core board, where a first circuit pattern including the bump pad is formed on one surface, a second circuit pattern electrically connected with the first circuit pattern is formed on the other surface, and a dielectric layer is selectively coated on the one surface such that the bump pad is exposed. The method includes layering a conductive layer on the other surface of the core board, coating a plating resist on the conductive layer, forming the bump by supplying electricity to the conductive layer to electroplate the bump pad, and removing the plating resist and the conductive layer. This makes it possible to omit the coining process and increase the density of the circuit by forming a fine bump by an electro tin plating method with small plating thickness deviation without designing additional plating bus lines, and improves the electrical performance without remaining plating bus lines.

    摘要翻译： 公开了封装基板的制造方法。 制造封装衬底的方法是通过在芯板上的凸块焊盘上形成凸块，其中在一个表面上形成包括凸点焊盘的第一电路图案，与第一电路图形电连接的第二电路图案形成在 另一表面和电介质层被选择性地涂覆在一个表面上，使得凸块焊盘露出。 该方法包括在芯板的另一个表面上层叠导电层，在导电层上涂覆电镀抗蚀剂，通过向导电层供电以形成凸块以电镀凸块焊盘，以及去除电镀抗蚀剂和导电层 。 这样可以省略压印过程，并且通过在不设计附加的电镀母线的情况下通过电镀镀层方法形成微小的凸起来提高电路的密度，并且不需要剩余的电镀母线即可提高电气性能。

    Multi-tap radio frequency modulator
    47.
    发明授权
    Multi-tap radio frequency modulator 失效
    多抽头射频调制器

    公开(公告)号：US6078784A

    公开(公告)日：2000-06-20

    申请号：US989588

    申请日：1997-12-12

    申请人： Jong Jin Lee

    发明人： Jong Jin Lee

    IPC分类号： H04N5/46 ,  H03C3/12 ,  H03D7/16 ,  H03H7/48 ,  H04N5/40 ,  H04H1/02

    CPC分类号： H04N5/40 ,  H03D7/161

    摘要： A multi-tap RF modulator includes an amplifier for amplifying a telecast RF signal input to an antenna input port; a modulation section for modulating the RF signal output from a VCR, SVR, or game player; and a mixer/splitter having more than one RF output tap and for mixing the first RF signal output from the amplifier and the second RF signal output from the modulation section, the mixed RF signals being distributed into more than one RF signal. The modulator with more than one output tap enables a user to view several TV sets at the same time.

    摘要翻译： 多抽头RF调制器包括用于放大输入到天线输入端口的电视射频信号的放大器; 用于调制从VCR，SVR或游戏者输出的RF信号的调制部分; 以及具有多于一个RF输出抽头并用于混合从放大器输出的第一RF信号和从调制部分输出的第二RF信号的混频器/分离器，混合RF信号被分配到多于一个RF信号中。 具有多个输出抽头的调制器使用户能够同时查看多个电视机。

    Method for manufacturing a capacitor for a semiconductor device
    48.
    发明授权
    Method for manufacturing a capacitor for a semiconductor device 失效
    半导体装置用电容器的制造方法

    公开(公告)号：US5443993A

    公开(公告)日：1995-08-22

    申请号：US347246

    申请日：1994-11-23

    申请人： Won-mo Park ,  Jong-jin Lee

    发明人： Won-mo Park ,  Jong-jin Lee

    IPC分类号： H01L27/04 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  Y10S148/014

    摘要： A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.

    摘要翻译： 一种半导体器件用电容器的制造方法，其特征在于，包括以下步骤：在半导体基板上形成第一导电层，通过图案化第一导电层形成第一图案，在第二导电层上依次形成第二导电层和第一材料层 通过各向异性蚀刻第一材料层在第二导电层的侧壁上形成间隔物，通过使用间隔物作为蚀刻掩模部分蚀刻第二导电层和第一图案来形成第二图案 在所得结构的整个表面上形成第三导电层，通过各向异性蚀刻第三导电层形成圆柱形的存储电极，并且去除间隔物。