公开(公告)号：US06605847B2

公开(公告)日：2003-08-12

申请号：US10039151

申请日：2002-01-03

Applicant: Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

Inventor： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC: H01L29786

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

公开(公告)号：US09368362B2

公开(公告)日：2016-06-14

申请号：US14284674

申请日：2014-05-22

Applicant: Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

Inventor： Sangho Rha ,  Jongmin Baek ,  Wookyung You ,  Sanghoon Ahn ,  Nae-In Lee

IPC: H01L21/311 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

Abstract translation: 提供了形成半导体器件的方法。 形成半导体器件的方法可以包括在金属图案上和在绝缘层的相邻部分上形成覆盖层，所述覆盖层包括相对于绝缘层在金属图案上的第一蚀刻选择性，第二 在绝缘层的部分上相对于绝缘层的蚀刻选择性。 此外，该方法可以包括通过从绝缘层的部分去除覆盖层来形成与金属图案相邻的凹陷区域。 在从绝缘层的部分去除覆盖层之后，覆盖层的至少一部分可以保留在金属图案的最上表面上。 还提供了相关的半导体器件。

公开(公告)号：US20160148930A1

公开(公告)日：2016-05-26

申请号：US15009276

申请日：2016-01-28

Applicant: Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20150214329A1

公开(公告)日：2015-07-30

申请号：US14680349

申请日：2015-04-07

Applicant: Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

Inventor： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US20150206974A1

公开(公告)日：2015-07-23

申请号：US14602660

申请日：2015-01-22

Applicant: Ha-Jin Lim ,  Hyeong-Joon Kim ,  Nae-In Lee

Inventor： Ha-Jin Lim ,  Hyeong-Joon Kim ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/20

CPC classification number: H01L29/66818 ,  H01L21/02241 ,  H01L21/28264 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

Abstract translation: 半导体器件包括包含III族元素和V族元素的半导体衬底，以及在半导体衬底上的栅极结构。 半导体衬底包括接触栅极结构的底表面的第一区域和设置在第一区域下方的第二区域。 第一区域中的III族元素的浓度低于第一区域中的V族元素的浓度，并且第二区域中的III族元素的浓度基本上等于第二区域中的第V族元素的浓度 地区。

公开(公告)号：US20150187763A1

公开(公告)日：2015-07-02

申请号：US14489900

申请日：2014-09-18

Applicant: Kug-Hwan Kim ,  Jong-Ho Lee ,  Woo-Hee Kim ,  Nae-In Lee

Inventor： Kug-Hwan Kim ,  Jong-Ho Lee ,  Woo-Hee Kim ,  Nae-In Lee

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/28202 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括包括第一至第四区域的衬底。 此外，第一至第四栅极绝缘层分别在第一至第四区域上。 在第一至第四栅极绝缘层中的功函数控制材料的量，第一至第四栅极绝缘层中的氮浓度和/或第一至第四栅极绝缘层的厚度在第一至第四栅极绝缘层之间变化。 还提供了制造半导体器件的方法。

公开(公告)号：US20140141589A1

公开(公告)日：2014-05-22

申请号：US14033639

申请日：2013-09-23

Applicant: Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

Inventor： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。 所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。 第二沟槽可以包括有源区的切口部分。

公开(公告)号：US08232613B2

公开(公告)日：2012-07-31

申请号：US12926227

申请日：2010-11-03

Applicant: Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

Inventor： Chang-wook Moon ,  Hyun-deok Yang ,  Joong S. Jeon ,  Hwa-sung Rhee ,  Nae-in Lee ,  Weiwei Chen

IPC: H01L31/119

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

Abstract translation: 示例性实施例涉及形成锗（锗）硅化物层的方法，包括锗硅化物层的半导体器件以及制造半导体器件的方法。 根据示例性实施方案的形成锗硅化物层的方法可以包括在硅锗（SiGe）层上形成包括钒（V）的金属层。 金属层可以具有多层结构，并且还可以包括铂（Pt）和镍（Ni）中的至少一种。 金属层可以退火以形成硅化锗层。 可以使用激光尖峰退火（LSA）方法进行退火。

公开(公告)号：US07595253B2

公开(公告)日：2009-09-29

申请号：US11797827

申请日：2007-05-08

Applicant: II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

Inventor： II-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

IPC: H01L21/76

CPC classification number: H01L21/31053 ,  H01L21/76229

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract translation: 示例性实施例提供半导体器件及其形成方法。 根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。 封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。 结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

公开(公告)号：US07494940B2

公开(公告)日：2009-02-24

申请号：US11333741

申请日：2006-01-17

Applicant: Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/00

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

Abstract translation: 可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理， 或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。