公开(公告)号：US20120184079A1

公开(公告)日：2012-07-19

申请号：US13428900

申请日：2012-03-23

Applicant: Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

Inventor： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC: H01L21/336

CPC classification number: H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

Abstract translation: 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US20120091469A1

公开(公告)日：2012-04-19

申请号：US13271615

申请日：2011-10-12

Applicant: Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

Inventor： Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

IPC: H01L29/772

CPC classification number: H01L29/66621 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

Abstract translation: 提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层 形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。

公开(公告)号：US08008698B2

公开(公告)日：2011-08-30

申请号：US12198266

申请日：2008-08-26

Applicant: Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

Inventor： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

Abstract: A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

Abstract translation: 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

公开(公告)号：US20090121268A1

公开(公告)日：2009-05-14

申请号：US12198266

申请日：2008-08-26

Applicant: Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

Inventor： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

Abstract: A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

Abstract translation: 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

公开(公告)号：US20090049786A1

公开(公告)日：2009-02-26

申请号：US11569820

申请日：2006-10-20

Applicant: Sung-Chul Hwang ,  Seung-Baik Nam ,  Seung-Hun Lee ,  Jong-Bum Kim ,  Jae-Wan Sung

Inventor： Sung-Chul Hwang ,  Seung-Baik Nam ,  Seung-Hun Lee ,  Jong-Bum Kim ,  Jae-Wan Sung

IPC: E04F15/10 ,  B32B3/10 ,  B05D3/12 ,  E04B5/02

CPC classification number: B32B21/00 ,  Y10T428/24802 ,  Y10T428/24851

Abstract: Disclosed herein is a low-priced flooring comprising a transfer-printed high-density fiberboard (HDF). According to the flooring, an aqueous primer layer is formed on a high-density fiberboard as a core layer and transfer printing is performed on the surface of the primer layer to form a printed layer so that the background fiber pattern of the high-density fiberboard is covered, the adhesion of the core layer to the printed layer is enhanced, and the natural beauty of wood is faithfully imparted to the surface of the flooring.

Abstract translation: 本文公开了包括转印印刷的高密度纤维板（HDF）的低价地板。 根据地板，在作为芯层的高密度纤维板上形成水性底漆层，在底漆层的表面进行转印，形成印刷层，使高密度纤维板的背景纤维图案 被覆盖，芯层与印刷层的粘附性增强，木材的自然美丽被忠实地赋予了地板表面。

公开(公告)号：US5901190A

公开(公告)日：1999-05-04

申请号：US771538

申请日：1996-12-23

Applicant: Seung-Hun Lee

Inventor： Seung-Hun Lee

IPC: G06F1/10 ,  G06F12/00 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03L7/00 ,  H03L7/081 ,  H03K5/14

CPC classification number: H03L7/0814 ,  H03K5/131

Abstract: A digital locked loop circuit having a synchronous delay line, an input node for receiving an external clock signal, and an internal clock node for generating an internal clock signal synchronized with the external clock signal. The digital locked loop circuit includes; a delay buffer for generating a first clock signal by delaying the external clock signal by a predetermined time; a main delay for generating a second clock signal by delaying the first clock signal by a predetermined time; a first delay line consisting of a plurality of serially connected first unit delays, each of the plurality of first unit delays generating a first unit delay output signal by delaying the second clock signal by a predetermined unit length; a second delay line consisting of a plurality of serially connected second unit delays, each of the plurality of second unit delays generating a second unit delay output signal by delaying the first clock signal by a predetermined unit length; switching means for coupling the first clock signal to the internal clock node in response to an enable signal, the switching means having a plurality of switches, each of the plurality of switches connected between an output node of a corresponding second unit delay of the second delay line and the internal clock node; and phase comparing means for generating the enable signal for a predetermined switch of the plurality of switches when the first clock signal is in phase with at least one first unit delay output signal, the phase comparing means being connected between an output node of a first unit delay and an enable port of a corresponding switch of the plurality of switches of the switching means.

Abstract translation: 具有同步延迟线的数字锁定环电路，用于接收外部时钟信号的输入节点和用于产生与外部时钟信号同步的内部时钟信号的内部时钟节点。 数字锁相环电路包括： 延迟缓冲器，用于通过将外部时钟信号延迟预定时间来产生第一时钟信号; 用于通过将第一时钟信号延迟预定时间来产生第二时钟信号的主延迟; 由多个串联的第一单元延迟组成的第一延迟线，所述多个第一单元延迟中的每一个通过将所述第二时钟信号延迟预定单位长度来产生第一单位延迟输出信号; 由多个串联的第二单元延迟组成的第二延迟线，所述多个第二单元延迟中的每一个延迟通过将所述第一时钟信号延迟预定单位长度来产生第二单位延迟输出信号; 用于响应于使能信号将所述第一时钟信号耦合到所述内部时钟节点的开关装置，所述开关装置具有多个开关，所述多个开关中的每一个开关连接在所述第二延迟的对应的第二单位延迟的输出节点之间 线和内部时钟节点; 以及相位比较装置，用于当第一时钟信号与至少一个第一单位延迟输出信号同相时，产生用于多个开关的预定开关的使能信号，所述相位比较装置连接在第一单元的输出节点之间 延迟和所述开关装置的多个开关中的相应开关的使能端口。

公开(公告)号：US5728257A

公开(公告)日：1998-03-17

申请号：US646989

申请日：1996-05-08

Applicant: Seung-Hun Lee

Inventor： Seung-Hun Lee

IPC: B32B37/18 ,  B30B15/34

CPC classification number: B32B37/185 ,  B32B37/0053 ,  B32B2037/0061 ,  Y10T156/1741

Abstract: A pouch laminator used for coating both sides of a small-sized sheet such as a photograph or identification card with a vinyl film is disclosed. Two folding guide plates are hinged to front and rear sides of the laminator body, respectively. A pair of bearing units are placed inside the laminator body for bearing the heating and molding rollers. A tension member detachably mounted to the top of each bearing unit for elastically holding the heating and molding rollers. A power supply unit having an elastic piece is placed aside each bearing unit. The elastic piece is brought into contact with a terminal provided on an associated end of each heating roller. A flat or embossing roller may be used as the molding roller. The embossing roller has a knurled rolling surface, thus embossing both sides of a coated sheet.

Abstract translation: 公开了一种用于涂覆小尺寸片材的两侧的袋式层压机，例如具有乙烯基膜的照片或身份证。 两个折叠导向板分别铰接到层压机主体的前侧和后侧。 一对轴承单元放置在层压机内部，用于承载加热和成型辊。 张紧构件可拆卸地安装到每个轴承单元的顶部，用于弹性地保持加热和成型辊。 具有弹性片的电源单元放置在每个轴承单元的旁边。 弹性件与设置在每个加热辊的相关端上的端子相接触。 可以使用平坦或压花辊作为成型辊。 压花辊具有滚花滚动表面，从而压印涂布纸的两面。

公开(公告)号：US5590086A

公开(公告)日：1996-12-31

申请号：US580481

申请日：1995-12-29

Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

公开(公告)号：US5532578A

公开(公告)日：1996-07-02

申请号：US68546

申请日：1993-05-28

Applicant: Seung-Hun Lee

Inventor： Seung-Hun Lee

IPC: G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G11C11/413 ,  H03F1/30 ,  H03G3/02 ,  H03K19/00 ,  G05F3/16

CPC classification number: G11C5/147

Abstract: A reference voltage generating circuit for converting a first source voltage to a second source voltage includes a positive thermal compensation circuit connected between the first source voltage and ground voltage and having a positive thermal coefficient for positively compensating the second source voltage with respect to temperature variations, and a negative thermal compensation circuit responsive to the output of the positive thermal compensation circuit and having a negative thermal coefficient for negatively compensating the second source voltage with respect to temperature variations, wherein the positive and negative thermal coefficients counter-balance each other so as to stabilize the second source voltage.

Abstract translation: 用于将第一源电压转换为第二源电压的参考电压产生电路包括连接在第一源电压和地电压之间的正热补偿电路，并具有用于相对于温度变化积极补偿第二源极电压的正热系数， 以及负热补偿电路，其响应于正热补偿电路的输出并且具有用于相对于温度变化对第二源极电压进行负补偿的负热系数，其中正和负热系数相互平衡，以便 稳定第二源电压。

公开(公告)号：US5446697A

公开(公告)日：1995-08-29

申请号：US068547

申请日：1993-05-28

Applicant: Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

Inventor： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

IPC: G11C5/14 ,  H02M3/07 ,  G11C13/00

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

Abstract translation: 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。