公开(公告)号：US20110201195A1

公开(公告)日：2011-08-18

申请号：US13091801

申请日：2011-04-21

Applicant: Takashi KITAE ,  Seiichi NAKATANI ,  Seiji KARASHIMA ,  Yoshihisa YAMASHITA ,  Takashi ICHIRYU

Inventor： Takashi KITAE ,  Seiichi NAKATANI ,  Seiji KARASHIMA ,  Yoshihisa YAMASHITA ,  Takashi ICHIRYU

IPC: H01L21/283

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/1141 ,  H01L2224/11502 ,  H01L2224/11522 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/165 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29299 ,  H01L2224/29305 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29313 ,  H01L2224/29316 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/832 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/83886 ,  H01L2224/83887 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0264 ,  H05K2203/087 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/066 ,  H01L2924/06 ,  H01L2924/0675 ,  H01L2924/0695 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The invention involves mounting a solder resin composition (6) including a solder powder (5a) and a resin (4) on the first electronic component (2); arranging such that the connecting terminals (3) of the first electronic component (2) and the electrode terminals (7) of the second electronic component (8) are facing each other; ejecting a gas (9a) from a gas generation source (1) included in the first electronic component (2) by heating the first electronic component (2) and the solder resin composition; and inducing the flow of the solder powder (5a) in the solder resin composition (6) by inducing convection of the gas (9a) in the solder resin composition (6), and electrically connecting the connecting terminals (3) and the electrode terminals (7) by self-assembly on the connecting terminals (3) and the electrode terminals (7). Through this are provided a flip chip packaging method that enables connecting, with high connection reliability, electrode terminals of a semiconductor chip wired with narrow pitch and connecting terminals of a circuit board, and a bump formation method for packaging on a circuit board.

Abstract translation: 本发明涉及将包含焊料粉末（5a）和树脂（4）的焊料树脂组合物（6）安装在第一电子部件（2）上; 排列成使得第一电子部件（2）的连接端子（3）和第二电子部件（8）的电极端子（7）彼此面对; 通过加热第一电子部件（2）和焊料树脂组合物，从包括在第一电子部件（2）中的气体发生源（1）喷出气体（9a） 并且通过引起焊料树脂组合物（6）中的气体（9a）的对流而引起焊料粉末（5a）在焊料树脂组合物（6）中的流动，并将连接端子（3）和电极端子 （7）通过在连接端子（3）和电极端子（7）上的自组装。 通过这种方式提供了一种倒装芯片封装方法，其以高连接可靠性连接具有窄间距的半导体芯片的电极端子和电路板的连接端子，以及用于封装在电路板上的凸块形成方法。

公开(公告)号：US07977741B2

公开(公告)日：2011-07-12

申请号：US12939729

申请日：2010-11-04

Applicant: Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L29/786

CPC classification number: H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

Abstract translation: 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20110133137A1

公开(公告)日：2011-06-09

申请号：US13027498

申请日：2011-02-15

Applicant: Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita

Inventor： Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Yoshihiro Tomita

IPC: H01B1/22

CPC classification number: H01L24/81 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1141 ,  H01L2224/1152 ,  H01L2224/11524 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/293 ,  H01L2224/294 ,  H01L2224/73104 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0425 ,  H05K2203/087 ,  H05K2203/1178 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip mounting process wherein a semiconductor chip and a circuit substrate are electrically interconnected. The process includes the steps of preparing a semiconductor chip on which a first plurality of electrodes are formed and a circuit substrate on which a second plurality of electrodes are formed; supplying a composition onto a surface of the circuit substrate, such surface being provided with second plurality of electrodes; bringing the semiconductor chip into contact with a surface of said composition such that the first plurality of electrodes are opposed to the second plurality of electrodes; and heating the circuit substrate, and thereby electrical connections including a metal component constituting the metal particles dispersed in the composition are formed between the first plurality of electrodes and the second plurality of electrodes. Also, a thermoset resin layer is formed between the semiconductor chip and the circuit substrate.

Abstract translation: 一种倒装芯片安装工艺，其中半导体芯片和电路基板电连接。 该方法包括制备其上形成有第一多个电极的半导体芯片和形成有第二多个电极的电路基板的步骤; 在电路基板的表面上提供组合物，该表面设置有第二多个电极; 使所述半导体芯片与所述组合物的表面接触，使得所述第一多个电极与所述第二多个电极相对; 并且加热电路基板，从而在第一多个电极和第二多个电极之间形成包括构成分散在组合物中的金属颗粒的金属组分的电连接。 此外，在半导体芯片和电路基板之间形成热固性树脂层。

公开(公告)号：US07851281B2

公开(公告)日：2010-12-14

申请号：US12518602

申请日：2008-10-01

Applicant: Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L21/336

CPC classification number: H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

Abstract translation: 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20100283054A1

公开(公告)日：2010-11-11

申请号：US12681445

申请日：2009-07-30

Applicant: Koichi Hirano ,  Seiichi Nakatani ,  Tatsuo Ogawa ,  Takashi Ichiryu ,  Takeshi Suzuki

Inventor： Koichi Hirano ,  Seiichi Nakatani ,  Tatsuo Ogawa ,  Takashi Ichiryu ,  Takeshi Suzuki

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78651 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1266 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869

Abstract: There is provided a method for manufacturing a flexible semiconductor device characterized by comprising (i) a step of forming an insulating film on the upper surface of metal foil, (ii) a step of forming an extraction electrode pattern on the upper surface of the metal foil, (iii) a step of forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the extraction electrode pattern, (iv) a step of forming a sealing resin layer on the upper surface of the metal foil in such a manner that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) a step of forming electrodes by etching the metal foil, wherein the metal foil is used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). A TFT element can be fabricated by a simple process because the metal foil serving as the support need not be finally stripped off. Further, a high-temperature process can be introduced to the fabrication of the insulating film and the semiconductor layer because the metal foil is used as the support, whereby the TFT characteristic is improved.

Abstract translation: 提供了一种制造柔性半导体器件的方法，其特征在于包括：（i）在金属箔的上表面上形成绝缘膜的步骤，（ii）在金属的上表面上形成引出电极图案的步骤 箔，（iii）以半导体层与引出电极图案接触的方式在绝缘膜上形成半导体层的步骤，（iv）在所述绝缘膜的上表面上形成密封树脂层的步骤 金属箔以密封树脂层覆盖半导体层和引出电极图案，以及（v）通过蚀刻金属箔形成电极的步骤，其中金属箔用作绝缘膜的支撑体， （i）〜（iv）中形成的并用作（v）中的电极的构成材料的引出电极图案，半导体层和密封树脂层。 由于作为支撑体的金属箔不需要最终被剥离，所以可以通过简单的工艺制造TFT元件。 此外，由于使用金属箔作为支撑体，因此可以将绝缘膜和半导体层的制造引入高温处理，从而提高TFT特性。

公开(公告)号：US20100182144A1

公开(公告)日：2010-07-22

申请号：US12376661

申请日：2007-08-06

Applicant: Yoshihisa Yamashita ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Fumio Fukushima ,  Kuniaki Kiyosue

Inventor： Yoshihisa Yamashita ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Fumio Fukushima ,  Kuniaki Kiyosue

IPC: G08B1/08 ,  G06K19/077 ,  G06K19/06 ,  B32B38/10

CPC classification number: H01Q19/10 ,  G06K19/07749 ,  G06K19/07771 ,  H01Q1/2208 ,  H01Q17/00

Abstract: Provided is a RFID magnetic sheet to be attached to an IC tag. The RFID magnetic sheet is provided with a plurality of stripe arranged layers (11a, 11b) whereupon a plurality of magnetic stripes (12) composed of a metal magnetic material are arranged at intervals, and a resin film (10) interposed between the respective stripe arranged layers. The arrangement relationship between the stripe arranged layers is set so that the magnetic stripes on each of the stripe arranged layers intersect with the magnetic stripes on the other stripe arranged layer in a planar shape.

Abstract translation: 提供了要附接到IC标签的RFID磁性片。 RFID磁性片设置有多个条状布置层（11a，11b），由此间隔地布置由金属磁性材料构成的多个磁条（12），并且在相应条带之间插入树脂膜（10） 布置层。 设置条纹布置层之间的布置关系，使得每个条纹布置层上的磁条与另一个条纹布置层上的磁条以平面形状相交。

公开(公告)号：US07754529B2

公开(公告)日：2010-07-13

申请号：US11814337

申请日：2006-02-02

Applicant: Yoshihiro Tomita ,  Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Toshio Fujii

Inventor： Yoshihiro Tomita ,  Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Toshio Fujii

IPC: H01L21/00

CPC classification number: H05K3/3436 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/742 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1152 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0285 ,  Y02P70/613 ,  H01L2224/05599

Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically. It becomes more likely that the molten electrically conductive particles in the resin contact the connection terminals or the electrode terminals, whereby the molten electrically conductive particles self-assemble between the electrode terminals and the connection terminals that have a high wettability, making it possible to form connectors for establishing an electric connection between these terminals in a uniform manner.

Abstract translation: 在其中具有多个电极端子（21）的半导体芯片（20）设置成与具有多个连接端子（11）的布线板（10）相对的倒装芯片安装体中，连接 端子（11）和电极端子（21）电连接，在连接端子（11）和电极端子（21）之间提供包含导电颗粒（12）的树脂（13），导电颗粒（12） ）和树脂（13）被加热和熔化，并且施加振动以使其流动。 允许熔融的导电颗粒（12）在连接端子（11）和电极端子（21）之间自组装，从而形成将它们电连接的连接器（22）。 树脂中的熔融的导电性粒子更可能接触连接端子或电极端子，由此熔融的导电性粒子在电极端子和具有高润湿性的连接端子之间自组装，从而形成 用于以均匀的方式在这些端子之间建立电连接的连接器。

公开(公告)号：US20100012936A1

公开(公告)日：2010-01-21

申请号：US12518602

申请日：2008-10-01

Applicant: Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8234 ,  B32B3/02

CPC classification number: H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

Abstract: A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

Abstract translation: 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20090203169A1

公开(公告)日：2009-08-13

申请号：US11814337

申请日：2006-02-02

Applicant: Yoshihiro Tomita ,  Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Toshio Fujii

Inventor： Yoshihiro Tomita ,  Koichi Hirano ,  Seiji Karashima ,  Takashi Ichiryu ,  Toshio Fujii

IPC: H01L21/60 ,  H01L21/768

CPC classification number: H05K3/3436 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/742 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1152 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83886 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/323 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0285 ,  Y02P70/613 ,  H01L2224/05599

Abstract: In a flip chip mounted body in which a semiconductor chip (20) having a plurality of electrode terminals (21) is disposed so as to be opposed to a wiring board (10) having a plurality of connection terminals (11), with the connection terminals (11) and the electrode terminals (21) being connected electrically, a resin (13) containing electrically conductive particles (12) is supplied between the connection terminals (11) and the electrode terminals (21), the electrically conductive particles (12) and the resin (13) are heated and melted, and vibrations are applied so as to make them flow. The molten electrically conductive particles (12) are allowed to self-assemble between the connection terminals (11) and the electrode terminals (21), thereby forming connectors (22) that connect them electrically. It becomes more likely that the molten electrically conductive particles in the resin contact the connection terminals or the electrode terminals, whereby the molten electrically conductive particles self-assemble between the electrode terminals and the connection terminals that have a high wettability, making it possible to form connectors for establishing an electric connection between these terminals in a uniform manner.

Abstract translation: 在其中具有多个电极端子（21）的半导体芯片（20）设置成与具有多个连接端子（11）的布线板（10）相对的倒装芯片安装体中，连接 端子（11）和电极端子（21）电连接，在连接端子（11）和电极端子（21）之间提供含有导电颗粒（12）的树脂（13），导电颗粒（12） ）和树脂（13）被加热和熔化，并且施加振动以使其流动。 允许熔融的导电颗粒（12）在连接端子（11）和电极端子（21）之间自组装，从而形成将它们电连接的连接器（22）。 树脂中的熔融的导电性粒子更可能接触连接端子或电极端子，由此熔融的导电性粒子在电极端子和具有高润湿性的连接端子之间自组装，从而形成 用于以均匀的方式在这些端子之间建立电连接的连接器。

公开(公告)号：US20090008800A1

公开(公告)日：2009-01-08

申请号：US11909856

申请日：2006-03-14

Applicant: Seiichi Nakatani ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Seiji Karashima

Inventor： Seiichi Nakatani ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Seiji Karashima

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/83007 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/0695 ,  H01L2224/05599

Abstract: The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217). Thereby, the flip chip mounted body with excellent productivity and reliability that can mount the semiconductor chip on the circuit board, and a method and an apparatus for mounting the flip chip mounted body are provided.

Abstract translation: 本发明的倒装芯片安装体包括：具有多个连接端子（211​​）的电路板（213）; 具有与所述连接端子相对设置的多个电极端子（207）的半导体芯片（206）。 在所述半导体芯片（206）的外周折叠具有设置在所述半导体芯片（206）的所述电极端子（207）的形成面的相反侧的盒状的多孔片（205） 在电极端子（207）的形成面侧与电路基板（213）接触，电路基板（213）的连接端子（211​​）和半导体芯片的电极端子（207） 206）通过焊料层（215）电连接，并且电路板（213）和半导体芯片（206）由树脂（217）固定。 因此，提供了将半导体芯片安装在电路板上的优异的生产率和可靠性的倒装芯片安装体以及安装倒装芯片安装体的方法和装置。