公开(公告)号：US11749658B2

公开(公告)日：2023-09-05

申请号：US17842678

申请日：2022-06-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ji Hye Lee ,  Kyung Bae Kim ,  Mee Hye Jung

IPC: H01L25/16 ,  H01L33/62 ,  H01L27/12 ,  H01L33/60 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L24/92 ,  H01L27/124 ,  H01L27/1259 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/9201 ,  H01L2224/92144 ,  H01L2933/0066

Abstract: A display device includes a substrate including a display area having a plurality of pixel areas and a non-display area located at at least one side of the display area; a pixel in each of the pixel areas; and a plurality of fan-out lines in the non-display area to form a first conductive layer. The pixel includes a pixel circuit layer including at least one transistor and a first bridge line and a second bridge line; and a display element layer on the pixel circuit layer. Each of the first and second bridge lines is electrically connected to a corresponding fan-out line from among the fan-out lines.

公开(公告)号：US20140328039A1

公开(公告)日：2014-11-06

申请号：US14347035

申请日：2012-09-25

Applicant: ALPHA METALS, INC.

Inventor： Paul J. Koep ,  Michiel A. de Monchy ,  Ellen S. Tormey

IPC: H05K13/04 ,  H05K1/09 ,  H05K1/11 ,  H01L23/00

CPC classification number: H05K13/0465 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16113 ,  H01L2224/1624 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/9201 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2076 ,  H05K1/092 ,  H05K1/111 ,  H05K3/3421 ,  H05K3/3478 ,  H05K3/3484 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2203/0405 ,  Y02P70/613

Abstract: In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.

Abstract translation: 根据一个或多个方面，减少焊接接头中的空隙形成的方法可以包括将焊膏沉积物施加到基板上，将焊料预制件放置在焊膏沉积物中，在焊料预制件上设置装置和焊膏 沉积和处理焊膏沉积物和焊料预制件以形成器件和衬底之间的焊接接头。 在一些方面，衬底是印刷电路板，并且该器件是集成电路封装。

公开(公告)号：US07626262B2

公开(公告)日：2009-12-01

申请号：US11424150

申请日：2006-06-14

Applicant: Ralf Otremba ,  Xaver Schloegel ,  Josef Hoeglauer ,  Matthias Stecher

Inventor： Ralf Otremba ,  Xaver Schloegel ,  Josef Hoeglauer ,  Matthias Stecher

IPC: H01L23/48

CPC classification number: H01L23/13 ,  H01L23/492 ,  H01L24/33 ,  H01L24/37 ,  H01L24/39 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/83136 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/9201 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.

Abstract translation: 连接结构包括具有第一主表面的半导体管芯和具有第二主表面的导电衬底。 第二主表面的至少一部分被定位成面向第一主表面并与第一主表面间隔一定距离。 电沉积金属层在第一主表面和第二主表面之间延伸并且电连接第一主表面和第二主表面。

公开(公告)号：US07531890B2

公开(公告)日：2009-05-12

申请号：US11131253

申请日：2005-05-16

Applicant: Gu-Sung Kim

Inventor： Gu-Sung Kim

IPC: H01L29/40

CPC classification number: H01L23/3114 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/9201

Abstract: A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.

Abstract translation: 提供了多芯片封装（MCP）。 MCP包括多个层叠的半导体芯片，每个堆叠的半导体芯片包括芯片焊盘和覆盖芯片焊盘的第一绝缘层，该开口具有露出芯片焊盘的一部分的开口。 每个芯片还包括形成在第一绝缘层上的焊盘再分布线和覆盖焊盘再分配线的第二绝缘层。 通过芯片，第一绝缘层，焊盘再分布线和第二绝缘层形成通孔。 MCP还包括形成在最低半导体芯片的底部上的保护层。 保护层包括与最低半导体芯片的底部相对形成的导电焊盘。 导电棒从导电焊盘延伸穿过堆叠的半导体芯片的通孔，并且电连接到堆叠的半导体芯片的焊盘再分配线。

公开(公告)号：US20090085227A1

公开(公告)日：2009-04-02

申请号：US11914581

申请日：2006-05-09

Applicant: Tsukasa Shiraishi ,  Seiichi Nakatani ,  Seiji Karashima ,  Koichi Hirano ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Tsukasa Shiraishi ,  Seiichi Nakatani ,  Seiji Karashima ,  Koichi Hirano ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L23/552 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/83007 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83136 ,  H01L2224/83139 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/303 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10568 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/13111

Abstract: A flip chip mounting body in which a circuit substrate having a plurality of connection terminals and an electronic part (semiconductor chip) having a plurality of electrode terminals are aligned face to face with each other, with a resin composition composed of solder powder, a resin and a convection additive being sandwiched in between, while a means such as spacers is interposed in between so as to provide a uniform gap between the two parts, or the electronic part (semiconductor chip) is placed inside a plate-shaped member having two or more protruding portions, so that the solder powder is allowed to move through boiling of the convection additive and to be self-aggregated to form a solder layer, thereby electrically connecting the connection terminals and the electrode terminals; and a mounting method for such a mounting body.

Abstract translation: 一种倒装芯片安装体，其中具有多个连接端子的电路基板和具有多个电极端子的电子部件（半导体芯片）彼此面对面地对准，其中树脂组合物由焊料粉末，树脂 并且夹在其间的对流添加剂，同时诸如间隔物的装置插入其间，以便在两个部件之间提供均匀的间隙，或者将电子部件（半导体芯片）放置在具有两个或 更多的突出部分，使得焊料粉末能够通过对流添加剂的沸腾而移动并且自聚集形成焊料层，从而电连接连接端子和电极端子; 以及这种安装体的安装方法。

公开(公告)号：US06908785B2

公开(公告)日：2005-06-21

申请号：US10306931

申请日：2002-11-27

Applicant: Gu-Sung Kim

Inventor： Gu-Sung Kim

IPC: H01L23/12 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L25/10 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/3114 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/9201

Abstract: A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.

Abstract translation: 提供了多芯片封装（MCP）。 MCP包括多个堆叠的半导体芯片，每个堆叠的半导体芯片包括芯片焊盘和覆盖芯片焊盘的第一绝缘层，该开口具有露出芯片焊盘的一部分的开口。 每个芯片还包括形成在第一绝缘层上的焊盘再分布线和覆盖焊盘再分配线的第二绝缘层。 通过芯片，第一绝缘层，焊盘再分布线和第二绝缘层形成通孔。 MCP还包括形成在最低半导体芯片的底部上的保护层。 保护层包括与最低半导体芯片的底部相对形成的导电焊盘。 导电棒从导电焊盘延伸穿过堆叠的半导体芯片的通孔，并且电连接到堆叠的半导体芯片的焊盘再分配线。

公开(公告)号：US20230361073A1

公开(公告)日：2023-11-09

申请号：US17739415

申请日：2022-05-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/3128 ,  H01L21/563 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2224/92165 ,  H01L2224/3224 ,  H01L2224/33055 ,  H01L2224/3303 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29386 ,  H01L2224/06166 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/4846 ,  H01L2224/48464 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48091 ,  H01L2224/49097 ,  H01L2224/49052 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2924/15151 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: A method of manufacturing a WBGA package includes providing a carrier having a first surface and a second surface opposite to the first surface of the carrier, wherein the carrier has a through hole extending between the first surface and the second surface of the carrier; disposing an electronic component on the second surface of the carrier, wherein the electronic component includes a first bonding pad and a second bonding pad; and electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

公开(公告)号：US20160358886A1

公开(公告)日：2016-12-08

申请号：US15171364

申请日：2016-06-02

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Edward Fuergut ,  Joachim Mahler

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L23/44 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/071 ,  H01L2224/291 ,  H01L2224/32227 ,  H01L2224/3701 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40228 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/831 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/848 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/9201 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/15151 ,  H01L2924/15153 ,  H05K7/023 ,  H05K7/08 ,  H05K7/10 ,  H05K7/20 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83

Abstract: A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.

Abstract translation: 半导体功率装置包括具有第一表面和与第一表面相对的第二表面的芯片载体。 半导体功率布置还包括附接到芯片载体的多个功率半导体芯片，其中功率半导体芯片倾斜于芯片载体的第一和/或第二表面。

公开(公告)号：US20160329290A1

公开(公告)日：2016-11-10

申请号：US15212603

申请日：2016-07-18

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Michael Newman ,  Terrence Caskey

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/14517 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/9201 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/30 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2224/05552

Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

Abstract translation: 本文公开了微电子组件及其制造方法。 在一个实施例中，形成微电子组件的方法包括组装第一和第二部件以使第一和第二部件的第一主表面彼此面对并且彼此隔开预定间隔，第一部件具有第一和第二相对 主表面，在第一和第二主表面之间沿第一方向延伸的第一厚度和在第一主表面处的多个第一金属连接元件，第二部件在第一主要部分具有多个第二金属连接元件 第二部件的表面; 以及电镀多个金属连接器区域，每个金属连接器区域在第一方向上在相应的第一连接元件和与相应的第一连接元件相对的相应的第二连接元件之间连续延伸。

公开(公告)号：US09093456B2

公开(公告)日：2015-07-28

申请号：US14519832

申请日：2014-10-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/48 ,  H01L25/00 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract translation: 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 壳体通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。