公开(公告)号：US08733858B2

公开(公告)日：2014-05-27

申请号：US13562780

申请日：2012-07-31

Applicant: Chao-Jie Cai ,  Wei Liang ,  Yong Ma ,  Yu-Lin Liu

Inventor： Chao-Jie Cai ,  Wei Liang ,  Yong Ma ,  Yu-Lin Liu

IPC: A47B81/00

CPC classification number: G06F1/188

Abstract: A computer enclosure includes a computer case and a power supply tray. The computer case includes a side plate and a rear plate adjacent to the side plate. A clamping portion is located on the rear plate, and an opening is defined between the side plate and the rear plate. The power supply tray is attached to the opening and includes a clipping member. The clipping member includes a securing portion extending from the power supply tray and a clipping portion rotatably attached to the securing portion. The clipping portion is engaged with the clamping portion to secure the power supply tray to the computer case, and the clipping portion is rotatable relative to the rear plate to disengage the clipping portion from the clamping portion.

Abstract translation: 计算机外壳包括电脑外壳和电源托盘。 计算机外壳包括侧板和与侧板相邻的后板。 夹紧部分位于后板上，并且在侧板和后板之间限定开口。 供电托盘附接到开口并且包括夹持构件。 夹持构件包括从电源托盘延伸的固定部分和可旋转地附接到固定部分的夹持部分。 夹持部分与夹持部分接合，以将电源托盘固定到计算机机壳上，并且夹持部分可相对于后板旋转以使夹持部分与夹持部分脱离。

公开(公告)号：US20140139828A1

公开(公告)日：2014-05-22

申请号：US13806992

申请日：2012-11-27

Applicant: Yung-Yu Lin

Inventor： Yung-Yu Lin

IPC: G01N21/956

CPC classification number: G01N21/956 ,  G01N21/95607

Abstract: The present invention discloses a pattern matching method, which is used in measurement process for line width measuring machine, comprising: reading a standard pattern used for matching on the at least one predetermined position of a measured sample; respectively comparing each standard pattern of the measured sample with prestored multiple designed original images corresponding to the standard pattern; determining that the pattern matching is successful if the standard pattern on the measured sample successfully compares with at least one designed original image, and proceeding with the subsequent line width measurement process; otherwise, determining that the pattern matching is failed. The present invention also discloses a corresponding pattern matching method and a line width measuring machine. According to the embodiment of the present invention, it can improve the accuracy and the success rate of the pattern matching when measuring the line width.

Abstract translation: 本发明公开了一种用于线宽测量机的测量过程中的模式匹配方法，包括：读取用于在测量样品的至少一个预定位置上进行匹配的标准图案; 分别比较测量样品的每个标准图案与对应于标准图案的预先存储的多个设计的原始图像; 如果测量样本上的标准图案与至少一个设计的原始图像成功比较，并且进行随后的线宽测量过程，则确定图案匹配成功; 否则，确定模式匹配失败。 本发明还公开了一种相应的图案匹配方法和线宽测量机。 根据本发明的实施例，可以在测量线宽时提高模式匹配的精度和成功率。

公开(公告)号：US20140131653A1

公开(公告)日：2014-05-15

申请号：US13675923

申请日：2012-11-13

Applicant: FENG-MING LEE ,  YU-YU LIN ,  MING-HSIU LEE

Inventor： FENG-MING LEE ,  YU-YU LIN ,  MING-HSIU LEE

IPC: H01L45/00 ,  G11C11/00

CPC classification number: G11C11/00 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract translation: 可编程金属化器件包括在第一和第二电极之间串联的第一电极和第二电极以及电介质层，导电离子阻挡层和离子供给层。 在操作中，在电介质层中形成或破坏导电桥，以使用具有相同极性的偏置电压来表示数据值，从而能够使用二极管接入装置。 为了形成导电桥，施加足够高的偏压，使得离子将导电离子阻挡层穿透到电介质层中，然后形成细丝或桥。 为了破坏导电桥，施加相同极性的偏压，导致电流流过结构，同时离子流被导电离子阻挡层阻挡。 作为焦耳加热的结果，介电层中的任何桥分解。

公开(公告)号：US08710632B2

公开(公告)日：2014-04-29

申请号：US13606007

申请日：2012-09-07

Applicant: Tien-Wei Yu ,  Chin-Cheng Chien ,  I-Ming Lai ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Fong-Lung Chuang ,  Chin-I Liao ,  Kuan-Yu Lin

Inventor： Tien-Wei Yu ,  Chin-Cheng Chien ,  I-Ming Lai ,  Shin-Chi Chen ,  Chih-Yueh Li ,  Fong-Lung Chuang ,  Chin-I Liao ,  Kuan-Yu Lin

IPC: H01L21/02

CPC classification number: H01L21/02639 ,  C30B25/165 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.

Abstract translation: 一种制备化合物半导体外延结构的方法包括以下步骤。 首先，在基板上形成第一复合外延层。 然后，进行连续的外延沉积工艺以在第一复合外延层上形成第二化合物外延层，使得第二化合物外延层具有线性降低的金属浓度梯度。 之后，在第二复合外延层上形成半导体材料层。

公开(公告)号：US08698316B2

公开(公告)日：2014-04-15

申请号：US13190408

申请日：2011-07-25

Applicant: Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电焊盘; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US20140082575A1

公开(公告)日：2014-03-20

申请号：US13618519

申请日：2012-09-14

Applicant: Chi-Wei Hu ,  Kuan-Yu Lin ,  Wan-Chun Chen ,  Chin-Chou Liu

Inventor： Chi-Wei Hu ,  Kuan-Yu Lin ,  Wan-Chun Chen ,  Chin-Chou Liu

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F17/5081 ,  G06F2217/82

Abstract: A method comprises selecting a region from a layout pattern of an integrated circuit, wherein the region comprises a plurality of functional units, and wherein the functional units are not coupled to each other through a variety of connection components, identifying hot spots in the region using a first threshold and inserting a plurality of decoupling capacitors adjacent to the hot spots.

Abstract translation: 一种方法包括从集成电路的布局图案中选择区域，其中该区域包括多个功能单元，并且其中功能单元不通过各种连接部件彼此耦合，使用 第一阈值并且插入与所述热点相邻的多个解耦电容器。

公开(公告)号：US08650964B2

公开(公告)日：2014-02-18

申请号：US13473679

申请日：2012-05-17

Applicant: Wei-Min Qin ,  Cong-Xu Hu ,  Yu-Lin Liu

Inventor： Wei-Min Qin ,  Cong-Xu Hu ,  Yu-Lin Liu

IPC: G01B5/30 ,  G01B7/16 ,  G01L1/00 ,  G01N3/00

CPC classification number: G01D11/30 ,  G01M7/027

Abstract: A testing apparatus includes a retaining panel, a screw pole, two securing panels moveably attached to the screw pole, and two mounting members. Each of the two securing panels is slidably attached to the retaining panel. Each of the two mounting member is engaged with each of the two securing panels. The two securing panels are moveable relative to the screw pole for sandwiching an electronic device, and each of the two mounting member is engaged with the screw pole, for prevent the two securing panels from disengaged from the electronic device.

Abstract translation: 测试装置包括保持板，螺杆，可移动地附接到螺杆的两个固定板和两个安装构件。 两个固定面板中的每一个可滑动地附接到保持面板。 两个安装构件中的每一个与两个固定板中的每一个接合。 两个固定面板相对于用于夹持电子设备的螺杆可移动，并且两个安装构件中的每一个与螺钉杆接合，以防止两个固定板从电子设备脱离。

公开(公告)号：US20140042506A1

公开(公告)日：2014-02-13

申请号：US13570157

申请日：2012-08-08

Applicant: Fredrik Ramberg ,  Tse-Hua Lu ,  Tsun-Lai Hsu ,  Victor Chiang Liang ,  Chi-Feng Huang ,  Yu-Lin Wei ,  Shu Fang Fu

Inventor： Fredrik Ramberg ,  Tse-Hua Lu ,  Tsun-Lai Hsu ,  Victor Chiang Liang ,  Chi-Feng Huang ,  Yu-Lin Wei ,  Shu Fang Fu

IPC: H01L29/78 ,  H01L31/08 ,  H01L21/336

CPC classification number: H01L27/14614 ,  H01L27/14616 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/7838

Abstract: Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor.

Abstract translation: 公开了晶体管，其制造方法和图像传感器电路。 在一个实施例中，晶体管包括设置在工件中的掩埋沟道，设置在掩埋沟道上方的栅极电介质和设置在栅极电介质上的栅极层。 栅极层在晶体管的俯视图中包括I形状。

公开(公告)号：US20140009602A1

公开(公告)日：2014-01-09

申请号：US13700400

申请日：2012-07-19

Applicant: Yung-yu Lin ,  Qingping Wang

Inventor： Yung-yu Lin ,  Qingping Wang

IPC: G01C11/02

CPC classification number: G01C11/025 ,  G01B11/02 ,  G01B2210/56 ,  G01N21/95684

Abstract: A line-width measurement device and a measurement method using the same are disclosed. The line-width measurement device has a platform, an image capturing device and a color-mixing light source device. The image capturing device captures an image of a pattern under measurement in a measurement area of the platform. The color-mixing light source device correspondingly provides illumination to the measurement area. The color-mixing light source device has a plurality of monochromatic light sources and adjusts the brightness scale of each monochromatic light source according to the matching rate of the pattern under measurement and a standard pattern to provide suitable color-mixed lights for illumination. Therefore, the present invention can provide a better measurement environment to further enhance accuracy of line-width measurement.

Abstract translation: 公开了线宽测量装置及其测量方法。 线宽测量装置具有平台，图像捕获装置和混色光源装置。 图像捕获装置在平台的测量区域中捕获测量图案的图像。 混色光源装置相应地向测量区域提供照明。 混色光源装置具有多个单色光源，并且根据测量图案的匹配率和标准图案调整各单色光源的亮度，以提供合适的彩色混合光进行照明。 因此，本发明可以提供更好的测量环境，以进一步提高线宽测量的精度。

公开(公告)号：US08581386B2

公开(公告)日：2013-11-12

申请号：US13350690

申请日：2012-01-13

Applicant: Yu-Lin Yen ,  Shih-Ming Chen ,  Hsi-Chien Lin ,  Yu-Lung Huang ,  Tsang-Yu Liu

Inventor： Yu-Lin Yen ,  Shih-Ming Chen ,  Hsi-Chien Lin ,  Yu-Lung Huang ,  Tsang-Yu Liu

IPC: H01L23/04 ,  H01L23/12

CPC classification number: H01L31/0203 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L27/14685 ,  H01L31/048 ,  H01L2224/16 ,  H01L2924/1461 ,  Y02E10/50 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

Abstract translation: 本发明的一个实施例提供了一种芯片封装，其包括：半导体衬底，具有与器件区域相邻的器件区域和非器件区域; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域和所述非器件区域; 设置在所述半导体衬底和所述封装层之间以及所述间隔层和所述器件区域之间并围绕所述非器件区域的一部分的环形结构; 以及包括形成在间隔层或环结构中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。