公开(公告)号：US20140143475A1

公开(公告)日：2014-05-22

申请号：US13683569

申请日：2012-11-21

Applicant: APPLE INC.

Inventor： Yoav Kasorla ,  Eyal Gurgi

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F21/60 ,  G06F21/79 ,  G06F2221/2143 ,  G11C16/10 ,  G11C16/14 ,  G11C16/22

Abstract: A method includes, in a memory with multiple analog memory cells, storing one or more data pages in respective groups of the memory cells using a first programming configuration having a first storage speed. Upon receiving a request to securely erase a data page from the memory, one or more of the memory cells in a group that stores the data page are re-programmed using a second programming configuration having a second storage speed that is faster than the first storage speed.

Abstract translation: 一种方法包括在具有多个模拟存储器单元的存储器中，使用具有第一存储速度的第一编程配置在存储器单元的相应组中存储一个或多个数据页。 在接收到从存储器安全地擦除数据页面的请求时，使用具有比第一存储器快的第二存储速度的第二编程配置来重新编程存储数据页面的组中的一个或多个存储器单元 速度。

公开(公告)号：US20140119089A1

公开(公告)日：2014-05-01

申请号：US14147714

申请日：2014-01-06

Applicant: Apple Inc.

Inventor： Avraham Meir ,  Micha Anholt ,  Naftali Sommer ,  Eyal Gurgi

IPC: G11C27/00

CPC classification number: G11C27/005 ,  G06F11/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5647 ,  G11C2211/5648

Abstract: A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels.

Abstract translation: 一种用于数据存储的方法包括在第一编程阶段通过将该组中的存储器单元编程为一组初始编程级别来将第一数据存储在一组模拟存储器单元中。 在第一编程阶段之后的第二编程阶段，通过以下方式将第二数据存储在组中：将在第一编程阶段中编程的组中的存储器单元识别为初始编程的预定义部分子集中的相应电平 水平; 以及仅使用所述第二数据来编程所识别的存储器单元，以便将所识别的存储器单元中的至少一些设置为与所述初始编程级别不同的一个或多个附加编程级别。

公开(公告)号：US08547740B2

公开(公告)日：2013-10-01

申请号：US13734335

申请日：2013-01-04

Applicant: Apple Inc.

Inventor： Naftali Sommer ,  Ofir Shalvi ,  Uri Perlmutter ,  Oren Golov ,  Eyal Gurgi ,  Micha Anholt ,  Dotan Sokolov

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/04 ,  G11C8/20 ,  G11C11/5642 ,  G11C16/20 ,  G11C16/28 ,  G11C2211/5634

Abstract: A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Abstract translation: 一种用于操作包括多个模拟存储单元（32）的存储器（28）的方法包括：通过向单元写入第一存储值来将数据存储在存储器中。 从单元读取第二存储值，并且估计第二存储值的累积分布函数（CDF）。 处理估计的CDF以计算一个或多个阈值。 使用一个或多个阈值对单元执行存储器存取操作。

公开(公告)号：US10884855B1

公开(公告)日：2021-01-05

申请号：US16535115

申请日：2019-08-08

Applicant: Apple Inc.

Inventor： Eli Yazovitsky ,  Yonathan Tate ,  Michael Tsohar ,  Naftali Sommer ,  Eyal Gurgi

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04 ,  H04L1/00 ,  H03M13/00 ,  H03M13/11 ,  G06F9/30 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/409

Abstract: A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np·NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.

公开(公告)号：US20180203774A1

公开(公告)日：2018-07-19

申请号：US15409583

申请日：2017-01-19

Applicant: Apple Inc.

Inventor： Charan Srinivasan ,  Eyal Gurgi

IPC: G06F11/20 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34

CPC classification number: G06F11/2094 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/85 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2216/14

Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory that includes multiple memory cells arranged in multiple planes that each includes one or more blocks of the memory cells. The storage circuitry is configured to apply a multi-plane storage operation to multiple blocks simultaneously across the respective planes. In response to detecting that the multi-plane storage operation has failed, the storage circuitry is configured to apply a single-plane storage operation to one or more of the blocks that were accessed in the multi-plane storage operation, including a given block, and to identify the given block as a bad block if the single-plane operation applied to the given block fails. The storage circuitry is further configured to store data in the blocks that were accessed in the multi-plane operation but were not identified as bad blocks.

公开(公告)号：US20180074892A1

公开(公告)日：2018-03-15

申请号：US15265869

申请日：2016-09-15

Applicant: Apple Inc.

Inventor： Assaf Shappir ,  Eyal Gurgi

IPC: G06F11/10 ,  G11C11/22 ,  G11C29/52 ,  H03M13/29

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C11/22 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/451

Abstract: A memory controller includes an interface and circuitry. The interface is configured to communicate with a memory device, which includes multiple memory cells, and which applies refreshing to the memory cells by repeatedly inverting data stored in the memory cells. The circuitry is configured to store input data in a group of the memory cells, to read the stored input data from the group of the memory cells to produce read data, the read data has an actual polarity that is either un-inverted or inverted due to the refreshing of the memory cells in the group, to analyze the read data for identifying the actual polarity of the read data, and to recover the input data from the read data based on the identified actual polarity.

公开(公告)号：US20170177265A1

公开(公告)日：2017-06-22

申请号：US14975789

申请日：2015-12-20

Applicant: Apple Inc.

Inventor： Charan Srinivasan ,  Eyal Gurgi

IPC: G06F3/06 ,  G11C16/34 ,  G11C11/56

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3436 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: A method for data storage includes preparing first data having a first size for storage in a memory device that stores data having a nominal size larger than the first size, by programming a group of memory cells to multiple predefined levels using a one-pass program-and-verify scheme. The first data is combined with dummy data to produce first combined data having the nominal size, and is sent to the memory device for storage in the group. The dummy data is chosen to limit the levels to which the memory cells in the group are programmed to a partial subset of the predefined levels. In response to identifying second data to be stored in the group, the second data is combined with the first data to obtain second combined data having the nominal size, and is sent to the memory device for storage, in place, in the group.

公开(公告)号：US09672919B2

公开(公告)日：2017-06-06

申请号：US13867363

申请日：2013-04-22

Applicant: Apple Inc.

Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Shai Ojalvo

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  G06F1/30 ,  G11C5/14 ,  G11C16/22 ,  G11C16/30

CPC classification number: G11C16/10 ,  G06F1/30 ,  G11C5/148 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/22 ,  G11C16/225 ,  G11C16/30 ,  G11C16/34 ,  G11C27/005 ,  G11C2211/5641

Abstract: A method includes, in a memory including analog memory cells, storing first data in a group of the memory cells using a first type of storage command that writes respective analog values to the memory cells in the group. Second data is stored in the memory cells in the group, in addition to the first data, using a second type of storage command that modifies the respective analog values of the memory cells in the group. Upon detecting imminent interruption of electrical power to the memory during storage of the second data, a switch is made to perform an alternative storage operation that is faster than the second type of storage command and protects at least the first data from the interruption.

公开(公告)号：US09455040B2

公开(公告)日：2016-09-27

申请号：US14962333

申请日：2015-12-08

Applicant: Apple Inc.

Inventor： Yael Shur ,  Yoav Kasorla ,  Moshe Neerman ,  Naftali Sommer ,  Avraham Poza Meir ,  Etai Zaltsman ,  Eyal Gurgi ,  Meir Dalal

IPC: G11C16/14 ,  G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/349

Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

公开(公告)号：US09454429B2

公开(公告)日：2016-09-27

申请号：US14595578

申请日：2015-01-13

Applicant: Apple Inc.

Inventor： Shai Ojalvo ,  Eyal Gurgi ,  Micha Anholt

IPC: G06F11/10 ,  G11C29/00 ,  H03M13/00 ,  G11C7/10 ,  G11C5/00

CPC classification number: G06F11/1016 ,  G06F11/1004 ,  G06F11/1044 ,  G06F11/108 ,  G11C5/005 ,  G11C7/1006 ,  G11C2207/104

Abstract: A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group.