公开(公告)号：US20180129261A1

公开(公告)日：2018-05-10

申请号：US15647088

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： SAURABH GARG ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/325 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F9/3004 ,  G06F9/4411 ,  G06F9/4418 ,  G06F13/404 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4278 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/44

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US20180089118A1

公开(公告)日：2018-03-29

申请号：US15721485

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Radha Kumar Pulyala ,  Saurabh Garg ,  Karan Sanghi

IPC: G06F13/28 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/287 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

公开(公告)号：US20170286323A1

公开(公告)日：2017-10-05

申请号：US15271109

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1441 ,  G06F12/1081 ,  G06F2212/1052

Abstract: Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.

公开(公告)号：US20160103480A1

公开(公告)日：2016-04-14

申请号：US14879027

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

公开(公告)号：US11792307B2

公开(公告)日：2023-10-17

申请号：US16144992

申请日：2018-09-27

Applicant: Apple Inc.

Inventor： Cahya Adiansyah Masputra ,  Karan Sanghi ,  Mingzhe Zhang ,  Zeh-Chen Liu ,  Sandeep Nair

IPC: H04L69/16 ,  H04L69/163 ,  H04L69/164 ,  H04L12/46 ,  G06F9/54 ,  H04L9/40 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10 ,  G06F13/16 ,  G06F3/06 ,  G06F9/46 ,  G06F12/02 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/6295 ,  H04L49/00 ,  H04L49/9047 ,  H04L69/00 ,  G06F9/455 ,  H04L47/193 ,  H04L47/283 ,  G06F9/52 ,  H04L43/0864 ,  G06F16/23 ,  G06F21/52 ,  H04L47/24 ,  H04L47/30 ,  H04L47/32 ,  H04L47/6275 ,  G06F21/56 ,  H04L69/22 ,  G06F16/22 ,  H04L61/103 ,  H04L61/2503 ,  H04L67/146 ,  H04L69/18 ,  H04L1/00

CPC classification number: H04L69/162 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0673 ,  G06F9/45558 ,  G06F9/461 ,  G06F9/4881 ,  G06F9/5005 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/52 ,  G06F9/542 ,  G06F9/545 ,  G06F12/023 ,  G06F12/10 ,  G06F13/1668 ,  G06F16/2228 ,  G06F16/2365 ,  G06F21/52 ,  G06F21/568 ,  H04L12/4641 ,  H04L43/0864 ,  H04L47/193 ,  H04L47/2458 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/283 ,  H04L47/30 ,  H04L47/32 ,  H04L47/6275 ,  H04L47/6295 ,  H04L49/30 ,  H04L49/9052 ,  H04L61/103 ,  H04L61/2542 ,  H04L63/166 ,  H04L67/146 ,  H04L69/02 ,  H04L69/161 ,  H04L69/163 ,  H04L69/164 ,  H04L69/18 ,  H04L69/22 ,  G06F9/50 ,  G06F2009/45595 ,  G06F2209/5011 ,  G06F2212/657 ,  G06F2221/032 ,  G06F2221/034 ,  H04L1/0061

Abstract: Methods and apparatus for efficient data transfer within a user space network stack. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional “socket” based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. Direct transfer reduces the per-byte and per-packet costs relative to socket based communication. A user space networking stack is disclosed that enables extensible, cross-platform-capable, user space control of the networking protocol stack functionality. The user space networking stack facilitates tighter integration between the protocol layers (including TLS) and the application or daemon. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack).

公开(公告)号：US11347567B2

公开(公告)日：2022-05-31

申请号：US16933826

申请日：2020-07-20

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F9/54 ,  G06F15/173 ,  G06F9/38

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

公开(公告)号：US11068326B2

公开(公告)日：2021-07-20

申请号：US16505446

申请日：2019-07-08

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/362 ,  H04L25/00 ,  G06F9/46 ,  G06F13/16 ,  H04W84/04 ,  H04W72/12

Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

公开(公告)号：US10789198B2

公开(公告)日：2020-09-29

申请号：US16450767

申请日：2019-06-24

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Saurabh Garg ,  Karan Sanghi ,  Haining Zhang

IPC: G06F15/17 ,  G06F13/42 ,  H04W4/80

Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

公开(公告)号：US10684670B2

公开(公告)日：2020-06-16

申请号：US16390998

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20200065161A1

公开(公告)日：2020-02-27

申请号：US16112383

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F9/38 ,  G06F15/173

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.