公开(公告)号：US20230067331A1

公开(公告)日：2023-03-02

申请号：US17896223

申请日：2022-08-26

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/15

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

公开(公告)号：US20220399457A1

公开(公告)日：2022-12-15

申请号：US17888894

申请日：2022-08-16

Applicant: Applied Materials, Inc.

Inventor： Steven C.H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11450759B2

公开(公告)日：2022-09-20

申请号：US17037941

申请日：2020-09-30

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  C30B29/06 ,  C30B29/52 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/56 ,  C23C16/455

Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US20220199804A1

公开(公告)日：2022-06-23

申请号：US17690193

申请日：2022-03-09

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US20220005937A1

公开(公告)日：2022-01-06

申请号：US17354251

申请日：2021-06-22

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20200220026A1

公开(公告)日：2020-07-09

申请号：US16818259

申请日：2020-03-13

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo ,  Benjamin Colombeau

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L21/822

Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.

公开(公告)号：US20200075332A1

公开(公告)日：2020-03-05

申请号：US16558719

申请日：2019-09-03

Applicant: Applied Materials, Inc.

Inventor： Johanes F. Swenberg ,  Abhishek Dube ,  Steven C.H. Hung ,  Benjamin Colombeau

IPC: H01L21/02 ,  H01L29/66

Abstract: A method of forming a silicon cap which comprises substantially no germanium atoms nor oxygen atoms is disclosed. Methods for controlling the oxidation of a silicon cap layer are also disclosed. Methods of forming a metal gate replacement which utilize the disclosed silicon cap and controlled oxidation are also disclosed.

公开(公告)号：US20200013878A1

公开(公告)日：2020-01-09

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L21/687

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US09853129B2

公开(公告)日：2017-12-26

申请号：US15242078

申请日：2016-08-19

Applicant: Applied Materials, Inc.

Inventor： Matthias Bauer ,  Hans-Joachim Ludwig Gossmann ,  Benjamin Colombeau

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/26 ,  H01L29/167 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02658 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/20 ,  H01L29/26 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

公开(公告)号：US12261047B2

公开(公告)日：2025-03-25

申请号：US17882177

申请日：2022-08-05

Applicant: Applied Materials, Inc.

Inventor： Wolfgang Aderhold ,  Yi-Chiau Huang ,  Wei Liu ,  Benjamin Colombeau ,  Abhilash Mayur

IPC: H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/02 ,  H10B41/27 ,  H10B43/27

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.