公开(公告)号：US11830729B2

公开(公告)日：2023-11-28

申请号：US17144972

申请日：2021-01-08

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/02112 ,  H01L21/02205

Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.

公开(公告)号：US11818877B2

公开(公告)日：2023-11-14

申请号：US17486631

申请日：2021-09-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang ,  Fredrick Fishburn ,  Gill Yong Lee ,  Nitin K. Ingle

IPC: H10B12/00

CPC classification number: H10B12/05 ,  H10B12/03 ,  H10B12/30

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

公开(公告)号：US11791155B2

公开(公告)日：2023-10-17

申请号：US17004262

申请日：2020-08-27

Applicant: Applied Materials, Inc.

Inventor： Huiyuan Wang ,  Susmit Singha Roy ,  Takehito Koshizawa ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/02 ,  H01L29/16

CPC classification number: H01L21/02304 ,  H01L21/02236 ,  H01L21/02362 ,  H01L21/02532 ,  H01L29/16

Abstract: Examples of the present technology include semiconductor processing methods to form diffusion barriers for germanium in a semiconductor structure. The methods may include forming a semiconductor layer stack from pairs of Si-and-SiGe layers. The Si-and-SiGe layer pairs may be formed by forming a silicon layer, and then forming the germanium barrier layer of the silicon layer. In some embodiments, the germanium-barrier layer may be less than or about 20 Å. A silicon-germanium layer may be formed on the germanium-barrier layer to complete the formation of the Si-and-SiGe layer pair. In some embodiments, the silicon layer may be an amorphous silicon layer, and the SiGe layer may be characterized by greater than or about 5 atom % germanium. Examples of the present technology also include semiconductor structures that include a silicon-germanium layer, a germanium-barrier layer, and a silicon layer.

公开(公告)号：US20220115263A1

公开(公告)日：2022-04-14

申请号：US17558848

申请日：2021-12-22

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US20210254210A1

公开(公告)日：2021-08-19

申请号：US17173871

申请日：2021-02-11

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: C23C16/40 ,  C23C16/52

Abstract: Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.

公开(公告)号：US10692880B2

公开(公告)日：2020-06-23

申请号：US15855465

申请日：2017-12-27

Applicant: Applied Materials, Inc.

Inventor： Zhenjiang Cui ,  Hanshen Zhang ,  Anchuan Wang ,  Zhijun Chen ,  Nitin K. Ingle

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/31 ,  H01L21/67 ,  H01L27/11556 ,  H01L23/29

Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes exposing a substrate having a multi-material layer formed thereon to radicals of a remote plasma to form one or more features through the multi-material layer, the one or more features exposing a portion of a top surface of the substrate, and the multi-material layer comprising alternating layers of a first layer and a second layer, wherein the remote plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about −100° C. to about 100° C.

公开(公告)号：US20200043734A1

公开(公告)日：2020-02-06

申请号：US16599447

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Mandar B. Pandit ,  Mang-Mang Ling ,  Tom Choi ,  Nitin K. Ingle

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/67

Abstract: Methods may be performed to limit footing, pitch walking, and other alignment issues. The methods may include forming a treatment gas plasma within a processing region of a semiconductor processing chamber. The methods may further include directing effluents of the treatment gas plasma towards a semiconductor substrate within the processing region of the semiconductor processing chamber, and anisotropically modifying a surface of a first material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may also include passivating a surface of a second material on the semiconductor substrate with the effluents of the treatment gas plasma. The methods may further include forming a remote fluorine-containing plasma to produce fluorine-containing plasma effluents, and flowing the fluorine-containing plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include selectively removing the modified surface of the first material from the semiconductor substrate.

公开(公告)号：US10354889B2

公开(公告)日：2019-07-16

申请号：US15651607

申请日：2017-07-17

Applicant: Applied Materials, Inc.

Inventor： Tom Choi ,  Mandar B. Pandit ,  Mang-Mang Ling ,  Nitin K. Ingle

IPC: H01L21/3105 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/3205

Abstract: Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide.

公开(公告)号：US20180240654A1

公开(公告)日：2018-08-23

申请号：US15957827

申请日：2018-04-19

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Yufei Zhu ,  Edwin C. Suarez ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Jiayin Huang

IPC: H01J37/32 ,  C23C16/44 ,  G01J3/02 ,  C23C16/50 ,  C23C16/52 ,  C23C16/455 ,  C23C16/452

CPC classification number: H01L21/32136 ,  C23C16/4405 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/50 ,  C23C16/52 ,  G01J3/0218 ,  G01J3/443 ,  H01J37/32082 ,  H01J37/32532 ,  H01J37/3255 ,  H01J37/32935 ,  H01J37/32963 ,  H01J37/32972 ,  H01J37/3299 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/67069 ,  H01L22/26

Abstract: In an embodiment, a plasma source includes a first electrode, configured for transfer of one or more plasma source gases through first perforations therein; an insulator, disposed in contact with the first electrode about a periphery of the first electrode; and a second electrode, disposed with a periphery of the second electrode against the insulator such that the first and second electrodes and the insulator define a plasma generation cavity. The second electrode is configured for movement of plasma products from the plasma generation cavity therethrough toward a process chamber. A power supply provides electrical power across the first and second electrodes to ignite a plasma with the one or more plasma source gases in the plasma generation cavity to produce the plasma products. One of the first electrode, the second electrode and the insulator includes a port that provides an optical signal from the plasma.

公开(公告)号：US09887096B2

公开(公告)日：2018-02-06

申请号：US14714050

申请日：2015-05-15

Applicant: Applied Materials, Inc.

Inventor： Seung H. Park ,  Yunyu Wang ,  Jingchun Zhang ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/3244 ,  H01L21/3065

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.