公开(公告)号：US07964967B2

公开(公告)日：2011-06-21

申请号：US12046737

申请日：2008-03-12

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.

Abstract translation: 用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。 接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

公开(公告)号：US07915056B2

公开(公告)日：2011-03-29

申请号：US12051868

申请日：2008-03-20

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Sambasivan Narayan ,  Anthony J. Perri ,  Richard J. Rassel ,  Tian Xia

IPC: G01R31/26

CPC classification number: H01L22/34 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract translation: 设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。 测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。 通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。 测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

公开(公告)号：US07821553B2

公开(公告)日：2010-10-26

申请号：US11275417

申请日：2005-12-30

Applicant: John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau ,  Richard J. Rassel

Inventor： John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Alain Loiseau ,  Richard J. Rassel

IPC: H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H04N9/083

CPC classification number: H04N9/045

Abstract: A pixel array in an image sensor, the image sensor and a digital camera including the image sensor. The image sensor includes a pixel array with colored pixels and unfiltered (color filter-free) pixels. Each unfiltered pixel occupies one or more array locations. The colored pixels may be arranged in uninterrupted rows and columns with unfiltered pixels disposed between the uninterrupted rows and columns. The image sensor may in CMOS with the unfiltered pixels reducing low-light noise and improving low-light sensitivity.

Abstract translation: 图像传感器中的像素阵列，图像传感器和包括图像传感器的数字照相机。 图像传感器包括具有彩色像素和未滤波（无滤色器）像素的像素阵列。 每个未过滤的像素占据一个或多个阵列位置。 彩色像素可以布置在不间断的行和列中，其中未过滤的像素布置在不间断的行和列之间。 图像传感器可以在CMOS中，未滤色像素降低低光噪声并改善低光灵敏度。

公开(公告)号：US20100230729A1

公开(公告)日：2010-09-16

申请号：US12538194

申请日：2009-08-10

Applicant: John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

Inventor： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

IPC: H01L27/148 ,  H01L27/146 ,  H01L31/0216 ,  H01L21/30 ,  G06F17/50

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

Abstract: CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate

Abstract translation: CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背面照明的光屏蔽 像素传感器单元。 在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽 遮光层。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器代替浮动扩散，并且被定位在载体衬底上的电介质隔离金属化堆叠中

公开(公告)号：US07719118B2

公开(公告)日：2010-05-18

申请号：US11838917

申请日：2007-08-15

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3157 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract translation: 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的方法。

公开(公告)号：US07655966B2

公开(公告)日：2010-02-02

申请号：US12050967

申请日：2008-03-19

Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Charles F. Musante ,  Richard J. Rassel

IPC: H04N3/14

CPC classification number: H04N5/361 ,  G06F17/5063 ,  H04N5/359 ,  H04N5/3745

Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

Abstract translation: 提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。 复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。 此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

公开(公告)号：US07633106B2

公开(公告)日：2009-12-15

申请号：US11164072

申请日：2005-11-09

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe

IPC: H01L31/00

CPC classification number: H01L27/14623 ,  H01L27/14685

Abstract: The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.

Abstract translation: 本发明提供一种用于屏蔽互补金属氧化物半导体（CMOS）成像器的浮动扩散的遮光罩。 根据本发明的实施例，提供了一种像素传感器单元，包括：形成在基板上的器件区域; 以及形成与所述器件区域的一侧相邻的侧壁的第一材料层，用于阻挡来自所述器件区域的电磁辐射。

公开(公告)号：US20090302406A1

公开(公告)日：2009-12-10

申请号：US12132875

申请日：2008-06-04

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

IPC: H01L31/00 ,  H01L21/00

CPC classification number: H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract translation: 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。

公开(公告)号：US07586139B2

公开(公告)日：2009-09-08

申请号：US11276218

申请日：2006-02-17

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alan Loiseau ,  Richard J. Rassel

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alan Loiseau ,  Richard J. Rassel

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14689

Abstract: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

Abstract translation: 具有FET像素阵列的成像传感器和形成成像传感器的方法。 每个像素是半导体岛，例如绝缘体上硅（SOI）晶片上的N型硅。 FET形成在一个光电二极管电极中，例如P阱阴极。 滤色器可以附接到岛的相对表面。 保护层（例如，玻璃或石英）或窗口在滤色器处固定到像素阵列。 图像传感器可以从背面照亮，电池布线在电池单元上方。 因此，通过保护层的光学信号被滤色器过滤并被相应的光电传感器选择性地感测。

公开(公告)号：US20090124047A1

公开(公告)日：2009-05-14

申请号：US12353549

申请日：2009-01-14

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/70

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。