公开(公告)号：US20080174021A1

公开(公告)日：2008-07-24

申请号：US12014458

申请日：2008-01-15

申请人： Kyung-In Choi ,  Hyun-Bae Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Kyung-In Choi ,  Hyun-Bae Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/52 ,  H01L21/4763 ,  C23C16/00

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device is provided. The method includes providing a semiconductor substrate having a conductive pattern and forming an insulating layer on the conductive pattern and the semiconductor substrate. The insulating layer is patterned to form an opening which exposes a portion of the conductive pattern. A preliminary diffusion barrier layer is formed on an inner wall of the opening and a top surface of the insulating layer. Oxygen atoms are supplied onto the preliminary diffusion barrier layer to form a first diffusion barrier layer. A metal layer is formed on the first diffusion barrier layer. The metal layer is formed to fill the opening surrounded by the first diffusion barrier layer. A semiconductor device fabricated by the method and a semiconductor cluster tool used in fabrication of the semiconductor device are also provided.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有导电图案的半导体衬底和在导电图案和半导体衬底上形成绝缘层。 图案化绝缘层以形成露出导电图案的一部分的开口。 在开口的内壁和绝缘层的上表面上形成预扩散阻挡层。 将氧原子提供到预扩散阻挡层上以形成第一扩散阻挡层。 金属层形成在第一扩散阻挡层上。 金属层形成为填充由第一扩散阻挡层包围的开口。 还提供了通过该方法制造的半导体器件和用于制造半导体器件的半导体簇工具。

公开(公告)号：US20080122076A1

公开(公告)日：2008-05-29

申请号：US11943166

申请日：2007-11-20

申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

IPC分类号： H01L23/48

CPC分类号： H01L27/115 ,  H01J2237/0812 ,  H01L27/11521 ,  H01L27/11524

摘要： A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.

摘要翻译： 在半导体衬底上设置有半导体衬底和多个下导电结构的半导体器件用导电布线。 提供了使多个下导电结构彼此电绝缘的绝缘层。 在绝缘层上设置第一绝缘夹层图案。 第一绝缘层间图案包括通过绝缘层接触衬底的接触插塞。 在接触插塞和第一绝缘层间图案上设置有蚀刻停止层。 在蚀刻停止层上设置第二绝缘层间图案。 第二绝缘层间图案包括电连接到接触插塞的导线。 还提供了相关方法和闪存设备。

公开(公告)号：US07279416B2

公开(公告)日：2007-10-09

申请号：US10796437

申请日：2004-03-09

申请人： Jung-hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-sook Park

发明人： Jung-hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-sook Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive structure is formed in an integrated circuit device by forming a lower conductive pattern on a substrate. A barrier metal layer is formed on the lower conductive pattern. The barrier metal layer is flushed with a gas that includes a halogen group gas and an upper conductive layer is formed on the barrier metal layer.

摘要翻译： 通过在基板上形成下导电图案，在集成电路器件中形成导电结构。 在下导电图案上形成阻挡金属层。 阻挡金属层用包含卤素气体的气体冲洗，并且在阻挡金属层上形成上导电层。

公开(公告)号：US07105444B2

公开(公告)日：2006-09-12

申请号：US10857253

申请日：2004-05-28

申请人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

发明人： Kyung-In Choi ,  Sang-Bom Kang ,  Seong-Geon Park ,  You-Kyoung Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Sang-Woo Lee

IPC分类号： H01L21/44

CPC分类号： H01L21/28556 ,  C23C16/34 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76877

摘要： In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1–C6 alkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

摘要翻译： 在使用原子层沉积形成半导体器件的布线的方法中，在基板上形成绝缘中间层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到绝缘中间层上。 一部分钽胺衍生物被化学吸附在绝缘中间层上。 在绝缘中间层上除去非化学吸附在绝缘中间层上的其余的钽胺衍生物。 将反应气体引入到绝缘中间层上。 化学吸附在绝缘中间层上的钽胺衍生物中的配体通过反应气体和配位体之间的化学反应从钽胺衍生物中除去以形成包括氮化钽的固体材料。 通过重复上述处理，将固体材料积聚在绝缘层间，形成布线。

公开(公告)号：US07098123B2

公开(公告)日：2006-08-29

申请号：US10780244

申请日：2004-02-17

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L21/28

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

摘要翻译： 形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。 金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。 形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

公开(公告)号：US07081409B2

公开(公告)日：2006-07-25

申请号：US10877848

申请日：2004-06-25

申请人： Sang-Bom Kang ,  Jong-Myeong Lee ,  Kyung-In Choi ,  Gil-Heyun Choi ,  You-Kyoung Lee ,  Seong-Geon Park ,  Sang-Woo Lee

发明人： Sang-Bom Kang ,  Jong-Myeong Lee ,  Kyung-In Choi ,  Gil-Heyun Choi ,  You-Kyoung Lee ,  Seong-Geon Park ,  Sang-Woo Lee

IPC分类号： H01L21/44

CPC分类号： H01L29/6659 ,  C23C16/34 ,  C23C16/56 ,  H01L21/265 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/823425 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

摘要： In a method for forming a gate electrode, a dielectric layer having a high dielectric constant is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR1)(NR2R3)3 in which R1, R2 and R3 represent H or C1–C6 alkyl group are introduced onto the dielectric layer to form a tantalum nitride layer. A capacitor metal layer or a gate metal layer is formed on the tantalum nitride layer. The capacitor metal layer or the gate metal layer and the tantalum nitride layer are patterned to form a capacitor electrode or a gate electrode. The tantalum amine derivatives are used in forming a dual gate electrode.

摘要翻译： 在形成栅电极的方法中，在基板上形成具有高介电常数的介电层。 由化学式Ta（NR 1）3（NR 2 R 3）3表示的钽胺衍生物，其中 R 1，R 2和R 3代表H或C 1 -C 6 >烷基引入到电介质层上以形成氮化钽层。 在氮化钽层上形成电容器金属层或栅极金属层。 将电容器金属层或栅极金属层和氮化钽层图案化以形成电容器电极或栅电极。 钽胺衍生物用于形成双栅电极。

公开(公告)号：US08969196B2

公开(公告)日：2015-03-03

申请号：US13616910

申请日：2012-09-14

申请人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

发明人： Jin-Ho Park ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Jong-Myeong Lee ,  Zung-Sun Choi ,  Hye-Kyung Jung

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L21/285 ,  H01L23/532 ,  H01L27/115 ,  H01L27/108

CPC分类号： H01L21/76846 ,  H01L21/28562 ,  H01L21/76856 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/10855 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

摘要翻译： 半导体器件可以包括在其上形成有多个下导电结构的基板上的绝缘层，其中绝缘层具有开口。 阻挡层位于绝缘层的开口的侧壁和底部上，其中阻挡层包括第一阻挡层，第一脱氧材料的成分比第一阻挡层中的金属材料更富，第二阻隔层 阻挡层，其中第二阻挡层中的金属材料比第二脱氧材料的成分更富。 互连在其开口中，侧壁和底部被阻挡层覆盖，互连电连接到下导电结构。

公开(公告)号：US08735265B2

公开(公告)日：2014-05-27

申请号：US13082861

申请日：2011-04-08

申请人： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

发明人： Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Jong-Myeong Lee

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  G02B6/13 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02675

摘要： A method of forming a silicon based optical waveguide can include forming a silicon-on-insulator structure including a non-crystalline silicon portion and a single crystalline silicon portion of an active silicon layer in the structure. The non-crystalline silicon portion can be replaced with an amorphous silicon portion and maintaining the single crystalline silicon portion and the amorphous portion can be crystallized using the single crystalline silicon portion as a seed to form a laterally grown single crystalline silicon portion including the amorphous and single crystalline silicon portions.

摘要翻译： 形成硅基光波导的方法可以包括在该结构中形成包括非晶硅部分和活性硅层的单晶硅部分的绝缘体上硅结构。 可以用非晶硅部分替代非晶硅部分，并且使用单晶硅部分作为种子来保持单晶硅部分和非晶部分可以结晶，以形成横向生长的单晶硅部分，其包括非晶态和 单晶硅部分。

公开(公告)号：US20120120728A1

公开(公告)日：2012-05-17

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US07972941B2

公开(公告)日：2011-07-05

申请号：US12165805

申请日：2008-07-01

申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

IPC分类号： H01L21/322

CPC分类号： H01L21/28176 ,  H01L21/76826 ,  H01L27/10855 ,  H01L27/11521

摘要： A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

摘要翻译： 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后，在层间绝缘层上直接形成氮化硅层，在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前，可以通过与基板接触的第一绝缘中间层形成插塞，并且金属布线可以电连接到插头。 插头可以包括钨。