公开(公告)号：US20120120728A1

公开(公告)日：2012-05-17

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung KIM ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US08547747B2

公开(公告)日：2013-10-01

申请号：US13191581

申请日：2011-07-27

申请人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Su-Kyoung Kim ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： G11C16/04

CPC分类号： H01L29/7926 ,  G11C5/063 ,  G11C16/0483 ,  H01L27/11582

摘要： A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.

摘要翻译： 提供了一种非易失性存储器件，包括由单晶半导体形成的衬底，垂直于衬底延伸的柱状半导体图案，多个栅极电极和与衬底垂直交替堆叠的多个层间电介质层，以及 形成在所述多个栅极电极和所述多个层间电介质层之间的电荷扩展阻挡层。

公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US08592979B2

公开(公告)日：2013-11-26

申请号：US13440123

申请日：2012-04-05

申请人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

发明人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/11524 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.

摘要翻译： 导电图案结构包括在基板上的第一绝缘中间层，第一绝缘中间层上的金属布线，金属布线上的第二绝缘中间层以及延伸穿过第二绝缘夹层的第一和第二金属触点。 第一金属触点与单元区域中的金属布线接触，并且第二金属触点与外围区域中的金属布线接触。 第三绝缘中间层设置在第二绝缘中间层上。 导电部分延伸通过电池区域中的第三绝缘中间层并与第一金属触点接触。 另一个导电段延伸穿过周边区域中的第三绝缘中间层并接触第二金属接触。 该结构有助于使用电镀工艺在电池区域中形成均匀厚的布线。

公开(公告)号：US08932964B2

公开(公告)日：2015-01-13

申请号：US13444054

申请日：2012-04-11

申请人： Woo-Jin Lee ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Hyun-Bae Lee

发明人： Woo-Jin Lee ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Hyun-Bae Lee

IPC分类号： H01L21/31 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.

摘要翻译： 一种形成电介质层的方法，所述方法包括通过执行等离子体增强原子层沉积工艺在衬底上顺序地形成第一氧化物层，氮化物层和第二氧化物层，其中第一氮等离子体处理在 形成第一氧化物层。

公开(公告)号：US07037828B2

公开(公告)日：2006-05-02

申请号：US10916303

申请日：2004-08-10

申请人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76841 ,  H01L21/7685 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.

摘要翻译： 半导体器件及其制造方法包括钴作为覆盖层。 半导体器件的互连结构具有改善的通孔电阻。 在半导体器件中，使用单个钴层或包含钴层和氮化钛层的复合膜作为金属层的覆盖层。

公开(公告)号：US20050046027A1

公开(公告)日：2005-03-03

申请号：US10916303

申请日：2004-08-10

申请人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Jung-Wook Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L21/4763 ,  H01L29/40

CPC分类号： H01L23/485 ,  H01L21/76841 ,  H01L21/7685 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.

摘要翻译： 半导体器件及其制造方法包括钴作为覆盖层。 半导体器件的互连结构具有改善的通孔电阻。 在半导体器件中，使用单个钴层或包含钴层和氮化钛层的复合膜作为金属层的覆盖层。

公开(公告)号：US20060281289A1

公开(公告)日：2006-12-14

申请号：US11446981

申请日：2006-06-06

申请人： Young-Cheon Kim ,  Chul Hwangbo ,  Rak-Hwan Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Young-Cheon Kim ,  Chul Hwangbo ,  Rak-Hwan Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/26513 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.

摘要翻译： 在形成多晶硅化合物层的方法和制造具有多晶硅化物层的半导体器件的方法中，该方法可以包括在具有第一区域和第二区域的衬底上形成掺杂有第一类型杂质的初步多晶硅层， 杂质进入第二区域的初步多晶硅层的一部分，热处理初步多晶硅层以电激活杂质，去除热处理的初步多晶硅层的上表面的一部分以获得多晶硅层，形成金属硅化物 并且在所述第一区域上形成所述多晶硅层和所述金属硅化物层以形成第一类型的栅电极，并在所述第二区域上形成第二类型的栅电极。

公开(公告)号：US06797618B2

公开(公告)日：2004-09-28

申请号：US10630570

申请日：2003-07-29

申请人： Eung-Joon Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Eung-Joon Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L2144

CPC分类号： H01L21/0206 ,  H01L21/02063 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/665 ,  Y10S438/906 ,  Y10S438/963

摘要： A conductive pattern having a surface including silicon is formed on a substrate of a semiconductor device and a conduction region having a surface including silicon is formed in the substrate. A radio frequency etching process is performed ex-situ to remove impurities from a resultant structure and to improve surface characteristics of the conduction region. Residues generated during the radio frequency etching process are removed from the conductive pattern and the conduction region by a cleaning process. A metal film is formed on the conductive pattern and the conduction region. A silicide film is formed on the conductive pattern and the conduction region by reacting metal of the metal film and silicon in the conductive pattern and the conduction region. With a radio frequency sputtering process and a wet cleaning process, a metal silicide film having a uniform phase may be stably formed.

摘要翻译： 在半导体器件的衬底上形成具有包括硅的表面的导电图案，并且在衬底中形成具有包括硅的表面的导电区域。 非原位地进行射频蚀刻处理以从所得结构中去除杂质并改善导电区域的表面特性。 在射频蚀刻工艺中产生的残留物通过清洁处理从导电图案和导电区域中去除。 在导电图案和导电区域上形成金属膜。 通过金属膜的金属和导电图案中的硅和导电区域之间的反应，在导电图案和导电区域上形成硅化物膜。 通过射频溅射法和湿式清洗法，可以稳定地形成具有均匀相的金属硅化物膜。