摘要:
A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.
摘要:
A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.
摘要:
Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
摘要:
Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
摘要:
In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.
摘要:
A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.
摘要:
A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.
摘要:
A semiconductor device, and a method of fabricating the same, includes cobalt as a capping layer. An interconnection structure of the semiconductor device has an improved via resistance. In the semiconductor device, a single cobalt layer or a composite film including a cobalt layer and a titanium nitride layer is used as the capping layer of a metal layer.
摘要:
An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.
摘要:
In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.