公开(公告)号：US10243074B2

公开(公告)日：2019-03-26

申请号：US15693938

申请日：2017-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L21/324 ,  H01L29/417

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

公开(公告)号：US20180240875A1

公开(公告)日：2018-08-23

申请号：US15954300

申请日：2018-04-16

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20180219079A1

公开(公告)日：2018-08-02

申请号：US15938412

申请日：2018-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

公开(公告)号：US20180197980A1

公开(公告)日：2018-07-12

申请号：US15913194

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

公开(公告)号：US09972682B2

公开(公告)日：2018-05-15

申请号：US15004756

申请日：2016-01-22

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Chun-chen Yeh

IPC: H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/265 ,  H01L29/45 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L29/0847 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

公开(公告)号：US20180102432A1

公开(公告)日：2018-04-12

申请号：US15693938

申请日：2017-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/324 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/7827 ,  H01L21/02614 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/41741 ,  H01L29/66553 ,  H01L29/66666

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

公开(公告)号：US09748352B2

公开(公告)日：2017-08-29

申请号：US14984688

申请日：2015-12-30

Applicant: STMicroelectronics, Inc. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

公开(公告)号：US09620505B2

公开(公告)日：2017-04-11

申请号：US15073100

申请日：2016-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L21/30 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.

公开(公告)号：US09564501B2

公开(公告)日：2017-02-07

申请号：US14581741

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

公开(公告)号：US09502518B2

公开(公告)日：2016-11-22

申请号：US14312418

申请日：2014-06-23

Applicant: STMicroelectronics, Inc. ,  Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract translation: 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是，当使用金属来形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分可以产生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。