公开(公告)号：US09136266B2

公开(公告)日：2015-09-15

申请号：US13943229

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/78

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract translation: 在各个方面，提供了形成半导体器件和半导体器件的方法。 在本文的一些说明性实施例中，硅/锗层设置在半导体衬底上。 在硅/锗层上形成至少一个绝缘材料层。 在进行热退火处理之后，在随后的处理顺序中除去至少一个绝缘材料层，使得硅/锗层至少部分暴露。 在随后施加的另外的处理顺序中，在暴露的硅/锗层上形成栅电极。

公开(公告)号：US09129843B1

公开(公告)日：2015-09-08

申请号：US14302880

申请日：2014-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka ,  Jan Hoentschel

IPC: H01F17/00 ,  H01L49/02 ,  H01L21/263 ,  H01L21/762 ,  H01L27/06 ,  H01L29/06 ,  B23K26/00 ,  B23K26/38

CPC classification number: H01L28/10 ,  B23K26/38 ,  B23K26/53 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0617 ,  H01L29/0653 ,  H01L29/66083 ,  H01L29/665 ,  H01L29/78 ,  H01L29/86

Abstract: A method of forming an inductor in a crystal semiconductor layer is provided, including generating an ion beam, directing the ion beam to a surface of the crystal semiconductor layer, applying a magnetic field to the ion beam to generate a helical motion of the ions and forming a three-dimensional helical structure in the crystal semiconductor layer by means of the ions of the ion beam.

Abstract translation: 提供一种在晶体半导体层中形成电感器的方法，包括产生离子束，将离子束引导到晶体半导体层的表面，向离子束施加磁场以产生离子的螺旋运动，以及 通过离子束的离子在晶体半导体层中形成三维螺旋结构。

公开(公告)号：US09123827B2

公开(公告)日：2015-09-01

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324 ,  H01L21/283 ,  H01L21/02

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20150200142A1

公开(公告)日：2015-07-16

申请号：US14153502

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann ,  Carsten Grass

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/823835 ,  H01L21/02595 ,  H01L21/28097 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Abstract translation: 一种用于制造集成电路的方法包括：在其上提供包括栅电极结构的半导体衬底和沿着所述栅电极结构的侧壁的侧壁间隔物，沿着所述侧壁形成第一高度，在所述栅电极结构上方形成平坦化碳基聚合物层，以及 并且蚀刻光学平坦化层的一部分以暴露栅电极结构的顶部。 此外，该方法包括蚀刻侧壁间隔物的上部，其选择性地选择栅电极结构，以便露出栅极电极结构的上部的侧壁并在栅电极结构的顶部上沉积硅化物形成材料 以及栅电极结构的上部的侧壁。 此外，该方法包括退火硅化物形成材料。

公开(公告)号：US20150111349A1

公开(公告)日：2015-04-23

申请号：US14579255

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L21/84 ,  H01L21/8234

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract translation: 一种结构包括半导体衬底，绝缘体上半导体区域和体区域。 绝缘体上半导体区域包括第一半导体区域，设置在半导体衬底和第一半导体区域之间的电介质层，以及包括设置在第一半导体区域中的有源区的第一晶体管。 电介质层在第一半导体区域和半导体衬底之间提供电隔离。 本体区域包括直接设置在半导体衬底上的第二半导体区域。

公开(公告)号：US20150050787A1

公开(公告)日：2015-02-19

申请号：US13965860

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Gerd Zschaetzsch ,  Jan Hoentschel

IPC: H01L29/66

CPC classification number: H01L21/28097 ,  H01L21/8238 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/6659

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 然而，完全硅化的栅极的形成受到源极和漏极区域以及栅极电极的硅化同时正常执行的事实的阻碍。 所要求保护的方法提出了两个相互连接的硅化过程。 在第一硅化工艺期间，形成金属硅化物，形成与源区和漏区的界面，而不影响栅电极。 在第二硅化处理期间，形成与栅电极具有界面的金属硅化物层，而不会影响晶体管的源极和漏极区域。

公开(公告)号：US08951873B2

公开(公告)日：2015-02-10

申请号：US13785480

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions.

Abstract translation: 提供了具有硅封装应力区域的半导体器件结构的装置和相关的制造方法。 一个半导体器件包括半导体衬底，覆盖半导体衬底的栅极结构，在栅极结构附近形成在半导体衬底中的应力区域以及覆盖在应力区域上的硅材料，所述硅材料封装应力区域。

公开(公告)号：US20140264349A1

公开(公告)日：2014-09-18

申请号：US14184863

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer ,  Alban Zaka

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

Abstract translation: 在本发明的方面，公开了一种形成半导体器件的方法，其中在制造期间的早期阶段形成非晶区域，并且非晶区域在随后的处理序列期间保守，并且提供具有非晶区域的中间半导体器件结构 在制造的早期阶段。 这里，在半导体衬底上提供栅极结构，并且在栅极结构附近形成非晶区。 源极/漏极延伸区域或源极/漏极区域形成在非晶区域中。 在一些说明性实施例中，可以将氟注入到非晶区域中。 在形成源极/漏极延伸区域和/或源极/漏极区域之后，执行快速热退火工艺。

公开(公告)号：US20140264347A1

公开(公告)日：2014-09-18

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US08786027B2

公开(公告)日：2014-07-22

申请号：US13886373

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L29/76 ,  H01L29/34 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract translation: 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。