公开(公告)号：US5787034A

公开(公告)日：1998-07-28

申请号：US813951

申请日：1997-03-03

申请人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

发明人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/16

摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。

公开(公告)号：US5636160A

公开(公告)日：1997-06-03

申请号：US570575

申请日：1995-12-11

申请人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

发明人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/16

摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。

公开(公告)号：US5592001A

公开(公告)日：1997-01-07

申请号：US626148

申请日：1996-04-05

申请人： Masamichi Asano

发明人： Masamichi Asano

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/349 ,  G11C11/5621 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/3495

摘要： There is disclosed a non-volatile semiconductor memory device wherein a pair of memory cells constituting one bit data memory unit are connected to a data line in a manner that their drains are commonly connected. When compared to the case where drains of two memory cells are respectively connected to different data lines, the number of the connecting portions between drains and data lines is reduced and the area required for connection is lessened. Thus, a semiconductor memory device satisfactorily miniaturized from the viewpoint of practical use is provided. Further, since there is employed an arrangement such that the one bit data memory unit is comprised of two (a pair of) memory cells, the reliability can be improved. Individual select transistors may be arranged between the drain common junctions in the pair of memory cells, respectively, or a common select transistor may be arranged therebetween. In addition, the sources of the two memory cells may be respectively formed as individual sources.

摘要翻译： 公开了一种非易失性半导体存储器件，其中构成一位数据存储器单元的一对存储单元以其漏极共同连接的方式连接到数据线。 当与两个存储单元的排水口分别连接到不同的数据线的情况相比，排水管和数据线之间的连接部分的数量减少，并且连接所需的面积减小。 因此，提供了从实用性的观点出发令人满意地小型化的半导体存储器件。 此外，由于采用一位数据存储单元由两个（一对）存储单元组成的布置，因此可以提高可靠性。 各个选择晶体管可以分别布置在一对存储单元中的漏极公共接头之间，或者可以在其间布置公共选择晶体管。 此外，两个存储单元的源可以分别形成为各个源。

公开(公告)号：US5153684A

公开(公告)日：1992-10-06

申请号：US734109

申请日：1991-07-24

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0425 ,  H01L27/115

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US4979146A

公开(公告)日：1990-12-18

申请号：US302712

申请日：1989-01-27

申请人： Sadayuki Yokoyama ,  Masamichi Asano ,  Hiroshi Iwahashi ,  Kaoru Nakagawa

发明人： Sadayuki Yokoyama ,  Masamichi Asano ,  Hiroshi Iwahashi ,  Kaoru Nakagawa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  H01L2924/0002

摘要： In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.

公开(公告)号：US4970686A

公开(公告)日：1990-11-13

申请号：US396246

申请日：1989-08-21

申请人： Yasuo Naruke ,  Thoru Mochizuki ,  Taira Iwase ,  Masamichi Asano

发明人： Yasuo Naruke ,  Thoru Mochizuki ,  Taira Iwase ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C17/12 ,  G11C17/14 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/785 ,  G11C17/12

摘要： A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

公开(公告)号：US4916334A

公开(公告)日：1990-04-10

申请号：US226312

申请日：1988-07-29

申请人： Hidenobu Minagawa ,  Yuuichi Tatsumi ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

发明人： Hidenobu Minagawa ,  Yuuichi Tatsumi ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

IPC分类号： G11C16/30 ,  H02M3/07 ,  H03K5/02

CPC分类号： G11C16/30 ,  H02M3/07 ,  H03K5/023

摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.

摘要翻译： 半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。 此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。

公开(公告)号：US4509148A

公开(公告)日：1985-04-02

申请号：US493605

申请日：1983-05-11

申请人： Masamichi Asano ,  Hiroshi Iwahashi

发明人： Masamichi Asano ,  Hiroshi Iwahashi

IPC分类号： G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C17/12 ,  G11C11/40

CPC分类号： G11C17/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C8/10

摘要： A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of said row decoders for controlling the conduction state of the switching MOS transistors.

摘要翻译： 半导体存储器电路包括多个半导体存储区域，连接到存储区域的多个数据线，用于相对于其传输数据;多条字线，用于将存取信号发送到存储区域;列解码器，连接到 所述多条数据线和行解码器具有分别连接到存储区域的解码部分和连接在解码器部分与电压供应端子之间的开关式MOS晶体管。 存储电路还包括连接到所述行解码器的开关MOS晶体管的存储器选择电路，用于控制开关MOS晶体管的导通状态。

公开(公告)号：US4447895A

公开(公告)日：1984-05-08

申请号：US192203

申请日：1980-09-30

申请人： Masamichi Asano ,  Hiroshi Iwahashi

发明人： Masamichi Asano ,  Hiroshi Iwahashi

IPC分类号： G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C17/12 ,  G11C11/40

CPC分类号： G11C17/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C8/10

摘要： A semiconductor memory circuit includes a plurality of semiconductor memory areas, a plurality of data lines connected to the memory areas for the transfer of data with respect thereto, a plurality of word lines for transmitting access signals to the memory areas, a column decoder connected to the plurality of data lines and a row decoder having decoding sections respectively connected to the memory areas and switching MOS transistors connected between the decoder sections and a voltage supply terminal. The memory circuit further includes a memory selection circuit connected to the switching MOS transistors of the row decoders for controlling the conduction state of the switching MOS transistors.

摘要翻译： 半导体存储器电路包括多个半导体存储区域，连接到存储区域的多个数据线，用于相对于其传输数据;多条字线，用于将存取信号发送到存储区域;列解码器，连接到 所述多条数据线和行解码器具有分别连接到存储区域的解码部分和连接在解码器部分与电压供应端子之间的开关式MOS晶体管。 存储电路还包括连接到行解码器的开关MOS晶体管的存储器选择电路，用于控制开关MOS晶体管的导通状态。

公开(公告)号：US20070279112A1

公开(公告)日：2007-12-06

申请号：US10589428

申请日：2005-02-09

申请人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

发明人： Kengo Maeda ,  Akira Tanigawa ,  Masuji Nishiyama ,  Shoichi Ohori ,  Makoto Hirano ,  Hiroshi Takashima ,  Shinji Matoba ,  Masamichi Asano

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222 ,  G11C16/32 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0818

摘要： A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay amount according to a signal from the phase comparison circuit comprises a means for inputting a first signal latched to a logic “1” by start of one clock cycle of the internal clock to the variable delay addition circuit through a dummy delay at the start of burst and a means for detecting the duration time of the logic “1” of the first signal inputted by the variable delay addition circuit through the dummy delay until one clock cycle of the internal clock is completed and setting the initial value of delay amount of the variable delay addition circuit based on the duration time.

摘要翻译： 使用具有用于比较内部时钟和延迟时钟的相位的相位比较电路的DLL电路的半导体存储器和用于根据来自相位比较电路的信号调整延迟量的可变延迟加法电路包括：用于输入第一信号的装置 通过在突发开始时的虚拟延迟，将内部时钟的一个时钟周期的开始锁存到逻辑“1”，并通过第一信号的逻辑“1”的持续时间检测装置 通过可变延迟加法电路通过虚拟延迟输入，直到内部时钟的一个时钟周期完成，并根据持续时间设定可变延迟加法电路的延迟量的初始值。