Air conditioning apparatus
    41.
    发明申请
    Air conditioning apparatus 审中-公开
    空调设备

    公开(公告)号:US20070066215A1

    公开(公告)日:2007-03-22

    申请号:US11491165

    申请日:2006-07-24

    IPC分类号: F24F13/06 B01D46/00 F25D17/04

    摘要: An air conditioning apparatus is provided. The air conditioning apparatus includes a cover assembly having an indoor air suction hole, a filter assembly cleaning indoor air sucked through the indoor air suction hole, and a grill. The grill includes a discharge grill formed on a side for discharging the indoor air cleaned by the filter assembly to an indoor area, and an exhaust grill for discharging indoor air to an outdoor area. A fan assembly draws indoor or outdoor air toward the grill. A rear panel is coupled to the grill. The rear panel includes a suction hole formed in one side for introducing outdoor air and an exhaust hole formed beside the suction hole for discharging indoor air to the outdoor area.

    摘要翻译: 提供一种空调装置。 该空气调节装置包括具有室内空气吸入孔的盖组件,清洁通过室内空气吸入孔吸入的室内空气的过滤器组件和格栅。 格栅包括形成在用于将由过滤器组件清洁的室内空气排放到室内的侧面的排放格栅和用于将室内空气排放到室外区域的排气格栅。 风扇组件将室内或室外空气朝向烤架抽吸。 后面板连接到格栅。 后面板包括形成在一侧的用于引入室外空气的吸入孔和形成在吸入孔旁边的用于将室内空气排放到室外区域的排气孔。

    Method and apparatus for processing JPEG data in mobile communication terminal
    42.
    发明申请
    Method and apparatus for processing JPEG data in mobile communication terminal 审中-公开
    用于处理移动通信终端中的JPEG数据的方法和装置

    公开(公告)号:US20060291730A1

    公开(公告)日:2006-12-28

    申请号:US11472584

    申请日:2006-06-21

    申请人: Ho Lee Jae Lee

    发明人: Ho Lee Jae Lee

    IPC分类号: G06K9/36

    CPC分类号: G09G5/391

    摘要: Provided is a device for resizing a JPEG image having a nonstandard size at a predetermined ratio to output the resized image on a display unit without distortion in a mobile communication terminal. A method for processing a JPEG image in a mobile communication terminal comprises extracting image sizes (X, Y) from JPEG data of a JPEG file stored in an image data storing unit, comparing display area sizes (dx, dy) of the display unit with the image sizes (X, Y), and resizing the image sizes (X, Y) while maintaining the ratio of width:length in consideration of the display area sizes (dx, dy) to output the resized image to the display unit.

    摘要翻译: 提供了一种用于在预定比例下调整具有非标准尺寸的JPEG图像的设备,以便在移动通信终端中在显示单元上输出调整大小的图像而不失真。 用于在移动通信终端中处理JPEG图像的方法包括从存储在图像数据存储单元中的JPEG文件的JPEG数据中提取图像尺寸(X,Y),将​​显示单元的显示区域大小(dx,dy)与 图像尺寸(X,Y),并且考虑到显示区域尺寸(dx,dy),同时保持宽度:长度的比例来调整图像尺寸(X,Y)的大小,以将调整大小的图像输出到显示单元。

    Bipolar device and method of manufacturing the same including pre-treatment using germane gas
    44.
    发明授权
    Bipolar device and method of manufacturing the same including pre-treatment using germane gas 失效
    双极装置及其制造方法,包括使用锗烷气体的预处理

    公开(公告)号:US07084041B2

    公开(公告)日:2006-08-01

    申请号:US10795175

    申请日:2004-03-05

    IPC分类号: H01L21/331

    摘要: A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

    摘要翻译: 一种制造双极器件的方法,其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里,在形成多晶硅层之前,使用锗烷气预处理单晶硅层。 因此,从单晶硅层去除氧化物层,并且在单晶硅层上形成锗层,从而防止Si重排。

    MOS transistor with elevated source/drain structure
    45.
    发明申请
    MOS transistor with elevated source/drain structure 有权
    具有升高的源极/漏极结构的MOS晶体管

    公开(公告)号:US20060163558A1

    公开(公告)日:2006-07-27

    申请号:US11388868

    申请日:2006-03-24

    IPC分类号: H01L31/109

    摘要: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

    摘要翻译: 在具有升高的源极/漏极结构的金属氧化物半导体(MOS)晶体管中,并且使用选择性外延生长(SEG)工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中,源极/漏极延伸结是 在形成外延层之后形成,从而防止源极/漏极结区域的劣化。 此外,源极/漏极延伸结部分由栅极层的下部部分地重叠,因为形成了两个栅极间隔物,并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

    Semiconductor devices having faceted channels and methods of fabricating such devices
    46.
    发明申请
    Semiconductor devices having faceted channels and methods of fabricating such devices 有权
    具有小平面通道的半导体器件和制造这种器件的方法

    公开(公告)号:US20060148154A1

    公开(公告)日:2006-07-06

    申请号:US11281599

    申请日:2005-11-18

    IPC分类号: H01L21/8234

    摘要: Disclosed are processes and techniques for fabricating semiconductor substrates for the manufacture of semiconductor devices, particularly CMOS devices, that include selectively formed, high quality single crystal or monocrystalline surface regions exhibiting different crystal orientations. At least one of the surface regions will incorporate at least one faceted epitaxial semiconductor structure having surfaces that exhibit a crystal orientation different than the semiconductor region on which the faceted epitaxial semiconductor structure is formed. According, the crystal orientation in the channel regions of the NMOS and/or PMOS devices may be configured to improve the relative performance of at least one of the devices and allow corresponding redesign of the semiconductor devices fabricated using such a process.

    摘要翻译: 公开了用于制造用于制造半导体器件,特别是CMOS器件的半导体衬底的工艺和技术,其包括具有不同晶体取向的选择性地形成的高质量单晶或单晶表面区域。 表面区域中的至少一个将结合至少一个具有不同于其上形成有刻面外延半导体结构的半导体区域的晶体取向的表面的分面外延半导体结构。 根据,NMOS和/或PMOS器件的沟道区域中的晶体取向可以被配置为改善至少一个器件的相对性能,并允许对使用这种工艺制造的半导体器件进行相应的重新设计。

    Method for manufacturing high-transmittance optical filter for image display devices
    47.
    发明申请
    Method for manufacturing high-transmittance optical filter for image display devices 有权
    用于制造用于图像显示装置的高透光率滤光器的方法

    公开(公告)号:US20060127818A1

    公开(公告)日:2006-06-15

    申请号:US11280393

    申请日:2005-11-17

    IPC分类号: G03F7/00

    摘要: A method for manufacturing a high-transmittance optical filter for image display devices, which may include the steps of coating a photocatalytic compound on a transparent substrate to form a photocatalytic film, selectively exposing the photocatalytic film to light and growing a metal crystal thereon by plating to form a metal pattern, and selectively etching and removing the photocatalytic compound remaining on the transparent substrate using a buffered oxide etchant (BOE). According to the method, a high-transmittance, high-resolution and low-resistivity optical filter can be manufactured in a simple manner at low costs.

    摘要翻译: 一种用于图像显示装置的高透光率滤光器的制造方法,其可以包括在透明基板上涂布光催化剂以形成光催化膜的步骤,选择性地将光催化膜曝光并通过电镀在其上生长金属结晶 以形成金属图案,并使用缓冲氧化物蚀刻剂(BOE)选择性地蚀刻和除去留在透明基板上的光催化化合物。 根据该方法,可以以低成本以简单的方式制造高透光率,高分辨率和低电阻率的滤光器。

    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device
    48.
    发明授权
    Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
    包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法

    公开(公告)号:US06987310B2

    公开(公告)日:2006-01-17

    申请号:US10851336

    申请日:2004-05-24

    摘要: A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

    摘要翻译: 半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。 异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。 在其界面处,异质外延层,即主外延层的底部,以及基板具有不同的晶格常数。 此外,中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。 中间外延层的厚度也小于主外延层的净厚度,使得中间外延层吸收异质外延层中的应变。 因此,可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

    Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same
    49.
    发明申请
    Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same 有权
    在使用其制造的单晶半导体和半导体器件上选择性地形成外延半导体层的方法

    公开(公告)号:US20050279997A1

    公开(公告)日:2005-12-22

    申请号:US11154236

    申请日:2005-06-16

    摘要: In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

    摘要翻译: 在单晶半导体上选择性地形成外延半导体层的方法和使用其制造的半导体器件的方法中,单晶外延半导体层和非单晶外延半导体层形成在单晶半导体和非单晶 半导体图案,分别使用主半导体源气体和主蚀刻气体。 使用选择性蚀刻气体去除非单晶外延半导体层。 主要气体和选择性蚀刻气体交替地和重复地供应至少两次以选择性地形成仅在单晶半导体上具有期望厚度的升高的单晶外延半导体层。 选择性蚀刻气体抑制在非单晶半导体图案上形成外延半导体层。

    Robust double-talk detection
    50.
    发明授权
    Robust double-talk detection 失效
    稳健的双方通话检测

    公开(公告)号:US5602913A

    公开(公告)日:1997-02-11

    申请号:US310614

    申请日:1994-09-22

    申请人: Ho Lee Budi Hardiman

    发明人: Ho Lee Budi Hardiman

    IPC分类号: H04B3/23 H04M9/08 H04M1/58

    CPC分类号: H04M9/082 H04B3/234

    摘要: A device and method for detecting and suppressing double-talk in a cellular mobile unit employ a cellular transceiver; a receive signal path; a transmit signal path; and a double-talk detector. The double-talk detector determines a receive slope of a receive signal, and determines a transmit slope of a transmit signal. The double-talk detector further determines a difference slope of a difference signal that is determined by evaluating differences between the receive signal and the transmit signal. Finally, the double-talk detector generates a double-talk flag signal in the event the transmit slope indicates an increasing transmit speech power, and the receive slope and the difference slope indicate a prescribed relationship between the changes in the receive speech power and the difference power.

    摘要翻译: 用于在蜂窝移动单元中检测和抑制双方通话的设备和方法采用蜂窝收发器; 接收信号路径; 发送信号路径; 和双向通话检测器。 双方通话检测器确定接收信号的接收斜率,并确定发送信号的发送斜率。 双方通话检测器还确定通过评估接收信号和发送信号之间的差异来确定的差分信号的差值斜率。 最后,在发送斜率表示增加的发送语音功率的情况下,双方通话检测器产生双方通话标志信号,接收斜率和差分斜率表示接收语音功率的变化与差异的规定关系 功率。