公开(公告)号：US10460067B2

公开(公告)日：2019-10-29

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/30 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L21/762 ,  H01L27/118

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

公开(公告)号：US10403627B2

公开(公告)日：2019-09-03

申请号：US15729532

申请日：2017-10-10

Applicant: IMEC vzw

Inventor： Jan Van Houdt ,  Julien Ryckaert ,  Hyungrock Oh

IPC: G11C5/06 ,  G11C5/02 ,  H01L23/528 ,  H01L27/108 ,  G11C11/405 ,  H01L21/8254 ,  G11C11/4097 ,  G11C13/00 ,  G11C5/04 ,  H01L25/065 ,  G11C11/4076 ,  H01L49/02 ,  G11C11/4094

Abstract: The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.

公开(公告)号：US10242907B2

公开(公告)日：2019-03-26

申请号：US15615299

申请日：2017-06-06

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Juergen Boemmels ,  Christopher Wilson

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

Abstract: A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the hard mask layer with a set of parallel material lines delimiting gaps therebetween; and (c) providing a spacer layer following the shape of the material layer. The method further includes (d) removing a top portion of the spacer layer, thereby forming spacer lines alternatively separated by material lines and by gaps; and (e) providing a blocking element in a portion of a gap. The method also includes (f) etching selectively the hard mask layer by using the material layer, the spacer lines and the blocking element as a mask, thereby providing a first set of parallel trenches in the hardmask layer, wherein a trench has a blocked portion; and (g) selectively removing the blocking element.

公开(公告)号：US10043798B2

公开(公告)日：2018-08-07

申请号：US15247127

申请日：2016-08-25

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Praveen Raghavan ,  Steven Demuynck ,  Julien Ryckaert

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L21/74 ,  H01L29/78

Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.

公开(公告)号：US20180174642A1

公开(公告)日：2018-06-21

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  G11C11/408 ,  H01L29/08 ,  H01L29/423

CPC classification number: G11C11/412 ,  G11C11/4085 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392

Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected. A source/drain of the pull-up transistor and of the pull-down transistor of the second stack, a source/drain of the pass transistor of the second stack and the common gate electrode of the pull-up and pull-down transistors of the first stack are electrically interconnected.

公开(公告)号：US20230361205A1

公开(公告)日：2023-11-09

申请号：US18298820

申请日：2023-04-11

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Bilal Chehab ,  Julien Ryckaert

IPC: H01L29/775 ,  H01L27/085 ,  H01L29/423 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L29/775 ,  H01L27/085 ,  H01L29/42392 ,  H01L29/0673 ,  H01L23/5286

Abstract: A standard cell semiconductor device is provided that includes a first and second FET device, each including: (i) a source body and a drain body, each including a common source or drain body portion and a set of source or drain prongs protruding from the common source or drain body portion, (ii) a set of channel layers, each channel layer extending between a pair of source and drain prongs, and (iii) a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion.

公开(公告)号：US20230178630A1

公开(公告)日：2023-06-08

申请号：US18061065

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Naoto Horiguchi ,  Julien Ryckaert

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545

Abstract: A method for forming a FET device is provided. The method includes: forming a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers; etching each of first and second fin parts from each of first and second opposite sides of the fin structure such that a set of source cavities extending through the first fin part is formed in a first set of layers of the layer stack, and such that a set of drain cavities extending through the second fin part is formed in the first set of layers of the layer stack; filling the source and drain cavities with a dummy material; while masking the fin structure from the second side: removing the dummy material by etching from the first side, and subsequently, forming a source body and a drain body, each comprising a respective common body portion and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively; and while masking the fin structure from the first side: etching a third fin part from the second side such that a set of gate cavities extending through the third fin part is formed in a second set of layers, and subsequently, forming a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US20230178554A1

公开(公告)日：2023-06-08

申请号：US18060785

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Bilal Chehab ,  Pieter Schuddinck ,  Julien Ryckaert ,  Pieter Weckx

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.

公开(公告)号：US11515399B2

公开(公告)日：2022-11-29

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US11201093B2

公开(公告)日：2021-12-14

申请号：US16836653

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.