公开(公告)号：US20200343085A1

公开(公告)日：2020-10-29

申请号：US16397795

申请日：2019-04-29

Applicant: Infineon Technologies AG

Inventor： Nirdesh Ojha ,  Roland Rupp ,  Francisco Javier Santos Rodriguez

IPC: H01L21/02 ,  H01L29/16 ,  B23H7/06 ,  B23H7/32 ,  B23H7/34 ,  B23H3/02

Abstract: A method includes producing a bulk substrate and beveling an edge of the bulk substrate using an electrical discharge machining (EDM) process and/or an electrochemical discharge machining (ECDM) process.

公开(公告)号：US10665687B2

公开(公告)日：2020-05-26

申请号：US15465688

申请日：2017-03-22

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Andreas Haertl ,  Francisco Javier Santos Rodriguez ,  André Rainer Stegner ,  Daniel Schloegl

IPC: H01L21/02 ,  H01L29/47 ,  H01L21/285 ,  H01L21/04

Abstract: A method for processing a semiconductor device in accordance with various embodiments may include: depositing a first metallization material over a semiconductor body; performing a heating process so as to form at least one region in the semiconductor body including a eutectic of the first metallization material and material of the semiconductor body; and depositing a second metallization material over the semiconductor body so as to contact the semiconductor body via the at least one region in the semiconductor body.

公开(公告)号：US10529612B2

公开(公告)日：2020-01-07

申请号：US15648543

申请日：2017-07-13

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Roland Rupp

IPC: H01L21/683 ,  B24B37/32 ,  H01L21/673 ,  H01L21/306

Abstract: In various embodiments, a method for processing a semiconductor wafer is provided. The semiconductor wafer includes a first main processing side and a second main processing side, which is arranged opposite the first main processing side, and at least one circuit region having at least one electronic circuit on the first main processing side. The method includes forming a stiffening structure, which at least partly surrounds the at least one circuit region and which stiffens the semiconductor wafer, wherein the stiffening structure has a cutout at least above part of the at least one circuit region, and thinning the semiconductor wafer, including the stiffening structure, from the second main processing side.

公开(公告)号：US20190295855A1

公开(公告)日：2019-09-26

申请号：US15935867

申请日：2018-03-26

Applicant: Infineon Technologies AG

Inventor： Nirdesh Ojha ,  Francisco Javier Santos Rodriguez

IPC: H01L21/326 ,  H01L21/304 ,  H01L21/288 ,  B23H7/26

Abstract: A method of structuring and/or thinning a semiconductor wafer having a plurality of functional chip sites includes forming one or more semiconductor devices in a device region of each functional chip site at a frontside of the semiconductor wafer, and forming an electrode at one of the frontside or a backside of the semiconductor wafer. The side of the semiconductor wafer at which the electrode is formed is structured by applying voltage pulses between the electrode and a tool electrode positioned above the semiconductor wafer as part of an electrical discharge machining (EDM) process before the electrode is removed by the EDM process, and between the tool electrode and an intrinsic conductive layer formed on the side of the semiconductor wafer being structured after the electrode is removed by the EDM process.

公开(公告)号：US10276656B2

公开(公告)日：2019-04-30

申请号：US15885340

申请日：2018-01-31

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Andre Brockmeier ,  Francisco Javier Santos Rodriguez ,  Daniel Schloegl ,  Hans-Joachim Schulze

IPC: H01L23/58 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/225 ,  H01L21/78

Abstract: Epitaxy troughs are formed in a semiconductor substrate, wherein a matrix section of the semiconductor substrate laterally separates the epitaxy troughs and comprises a first semiconductor material. Crystalline epitaxy regions of a second semiconductor material are formed in the epitaxy troughs, wherein the second semiconductor material differs from the first semiconductor material in at least one of porosity, impurity content or defect density. From the epitaxy regions at least main body portions of semiconductor bodies of the semiconductor devices are formed.

公开(公告)号：US20190078211A1

公开(公告)日：2019-03-14

申请号：US15700232

申请日：2017-09-11

Applicant: Infineon Technologies AG

Inventor： Matthias Kuenle ,  Johannes Baumgartl ,  Manfred Engelhardt ,  Christian Illemann ,  Francisco Javier Santos Rodriguez ,  Olaf Storbeck

IPC: C23C16/54 ,  C23C16/02 ,  C23C16/455 ,  H01L21/02

Abstract: A CVD reactor, including a deposition chamber housing a first susceptor and a second susceptor, the first susceptor having a cavity for receiving a first substrate, the first substrate having a front surface and a back surface, the second susceptor having a cavity for receiving a second substrate, the second substrate having a front surface and a back surface, and the first susceptor and the second susceptor are disposed so that the front surface of the first substrate is opposite to the front surface of the second substrate thereby forming a portion of a gas flow channel.

公开(公告)号：US09954068B2

公开(公告)日：2018-04-24

申请号：US14866157

申请日：2015-09-25

Applicant: Infineon Technologies AG

Inventor： Philip Christoph Brandt ,  Francisco Javier Santos Rodriguez ,  Andre Rainer Stegner

IPC: H01L29/423 ,  H01L21/02 ,  H01L29/78 ,  H01L29/739 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L21/02244 ,  H01L21/3086 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.

公开(公告)号：US09935060B2

公开(公告)日：2018-04-03

申请号：US15430582

申请日：2017-02-13

Applicant: Infineon Technologies AG

Inventor： Srinivasa Reddy Yeduru ,  Karl Heinz Gasser ,  Stefan Woehlert ,  Karl Mayer ,  Francisco Javier Santos Rodriguez

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/288

CPC classification number: H01L23/562 ,  H01L21/288 ,  H01L21/4814 ,  H01L21/6835 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/04026 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05687 ,  H01L2224/27002 ,  H01L2224/27005 ,  H01L2224/2732 ,  H01L2224/2747 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29021 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29393 ,  H01L2224/32245 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/04941 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05124 ,  H01L2224/05187 ,  H01L2924/0665 ,  H01L2924/01006 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/07802

Abstract: A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.

公开(公告)号：US20180019150A1

公开(公告)日：2018-01-18

申请号：US15648543

申请日：2017-07-13

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Roland Rupp

IPC: H01L21/683 ,  H01L21/306

Abstract: In various embodiments, a method for processing a semiconductor wafer is provided. The semiconductor wafer includes a first main processing side and a second main processing side, which is arranged opposite the first main processing side, and at least one circuit region having at least one electronic circuit on the first main processing side. The method includes forming a stiffening structure, which at least partly surrounds the at least one circuit region and which stiffens the semiconductor wafer, wherein the stiffening structure has a cutout at least above part of the at least one circuit region, and thinning the semiconductor wafer, including the stiffening structure, from the second main processing side.

公开(公告)号：US20170358452A1

公开(公告)日：2017-12-14

申请号：US15616117

申请日：2017-06-07

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Alexander Breymesser ,  Andre Brockmeier ,  Ronny Kern ,  Francisco Javier Santos Rodriguez ,  Carsten von Koblinski

IPC: H01L21/266 ,  H01L29/36 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L21/266 ,  H01J2237/31701 ,  H01L21/0465 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L29/36

Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body of the power semiconductor device; coupling a mask to the semiconductor body; and subjecting the semiconductor body to an ion implantation such that implantation ions traverse the mask prior to entering the semiconductor body.