公开(公告)号：US10402330B2

公开(公告)日：2019-09-03

申请号：US15944598

申请日：2018-04-03

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Mustafa Hajeer ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Benjamin Graniello

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0817

Abstract: Examples include a processor including a coherency mode indicating one of a directory-based cache coherence protocol and a snoop-based cache coherency protocol, and a caching agent to monitor a bandwidth of reading from and/or writing data to a memory coupled to the processor, to set the coherency mode to the snoop-based cache coherency protocol when the bandwidth exceeds a threshold, and to set the coherency mode to the directory-based cache coherency protocol when the bandwidth does not exceed the threshold.

公开(公告)号：US10389839B2

公开(公告)日：2019-08-20

申请号：US15170094

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Brian J. Slechta

IPC: H04L29/08 ,  G06F12/0862

Abstract: An apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of the prefetch request to the memory device and in response to a read request for at least a portion of the data set, request the at least a portion of the data set from a cache storing a copy of the data set, wherein the cache is to store the copy of the data set after the copy is received from the memory device in response to the prefetch request.

公开(公告)号：US10318417B2

公开(公告)日：2019-06-11

申请号：US15476866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/06 ,  G06F12/0873 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42

Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.

公开(公告)号：US20190171556A1

公开(公告)日：2019-06-06

申请号：US16204772

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Brian J. Slechta

IPC: G06F12/02 ,  G06F12/0893

Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.

公开(公告)号：US20190138361A1

公开(公告)日：2019-05-09

申请号：US16236196

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Ned Smith ,  Thomas Willhalm ,  Timothy Verrall

IPC: G06F9/50 ,  G06F9/455 ,  G06F1/26

Abstract: Technologies for providing dynamic selection of edge and local accelerator resources includes a device having circuitry to identify a function of an application to be accelerated, determine one or more properties of an accelerator resource available at the edge of a network where the device is located, and determine one or more properties of an accelerator resource available in the device. Additionally, the circuitry is to determine a set of acceleration selection factors associated with the function, wherein the acceleration factors are indicative of one or more objectives to be satisfied in the acceleration of the function. Further, the circuitry is to select, as a function of the one or more properties of the accelerator resource available at the edge, the one or more properties of the accelerator resource available in the device, and the acceleration selection factors, one or more of the accelerator resources to accelerate the function.

公开(公告)号：US10255305B2

公开(公告)日：2019-04-09

申请号：US15260618

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Thomas Willhalm ,  Karthik Kumar ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: G06F17/00 ,  G06F17/30 ,  H04L29/08 ,  G06F12/0804 ,  G06F12/0815

Abstract: Technologies for object-based data consistency in a fabric architecture includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an object read request that includes an object identifier and a data consistency threshold from one of the computing nodes. The network switch is additionally configured to perform a lookup for a value of an object in the cache memory as a function of the object identifier and determine whether a condition of the value of the object violates the data consistency threshold in response to a determination that the lookup successfully returned the value of the object. The network switch is further configured to transmit the value of the object to the computing node in response to a determination that the condition of the value of the object does not violate the data consistency threshold. Other embodiments are described herein.

公开(公告)号：US20180241802A1

公开(公告)日：2018-08-23

申请号：US15437565

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Gaspar Mora Porta ,  Daniel Rivas Barragan

IPC: H04L29/08 ,  H04L12/26

CPC classification number: H04L67/101 ,  H04L43/0894 ,  H04L67/1006 ,  H04L67/1012 ,  H04L67/1029

Abstract: Technologies for network switch based load balancing include a network switch. The network switch is to receive messages, route messages to destination computing devices, receive a request to perform a workload, and receive telemetry data from a plurality of server nodes in communication with the network switch. The telemetry data is indicative of a present load on one or more resources of each server node. The network switch is further to determine channel utilization data for each of the server nodes, select, as a function of the telemetry data and the channel utilization data, one or more of the server nodes to execute the workload, and assign the workload to the selected one or more server nodes. Other embodiments are also described and claimed.

公开(公告)号：US20180239725A1

公开(公告)日：2018-08-23

申请号：US15435886

申请日：2017-02-17

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Suleyman Sair ,  Francesc Guim Bernat ,  Thomas Willhalm ,  Daniel Rivas Barragan

IPC: G06F13/28 ,  G06F12/0891 ,  G06F3/06 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F12/0804 ,  G06F12/0897 ,  G06F13/4022 ,  G06F13/4068 ,  G06F2212/1032

Abstract: In an example, there is disclosed a computing apparatus, including: a host fabric interface (HFI) for communicatively coupling to a fabric controller of a fabric; an asynchronous data refresh (ADR) having an auxiliary power and an ADR buffer; and a memory controller including logic to: directly access a persistent fast memory of a remote computing device via the fabric; detect a primary power failure event; and flush data from the ADR buffer to the fabric controller.

公开(公告)号：US20180150240A1

公开(公告)日：2018-05-31

申请号：US15720236

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Mark A. Schmisseur ,  Thomas Willhalm

IPC: G06F3/06

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for offloading I/O intensive workload phases to a data storage sled include a compute sled. The compute sled is to execute a workload that includes multiple phases. Each phase is indicative of a different resource utilization over a time period. Additionally, the compute sled is to identify an I/O intensive phase of the workload, wherein the amount of data to be communicated through a network path between the compute sled and the data storage sled to execute the I/O intensive phase satisfies a predefined threshold. The compute sled is also to migrate the workload to the data storage sled to execute the I/O intensive phase locally on the data storage sled. Other embodiments as also described and claimed.

公开(公告)号：US09921840B2

公开(公告)日：2018-03-20

申请号：US15277702

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Thomas Willhalm ,  Garrett T. Drysdale

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30112 ,  G06F15/78

Abstract: Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a list of index values in response to a single vector packed convert a mask register into a list of index values instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.