公开(公告)号：US20180082965A1

公开(公告)日：2018-03-22

申请号：US15813342

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Brian M. Erwin ,  Brittany L. Hedrick ,  Nicholas A. Polomoff ,  TaeHo Kim ,  Matthew E. Souter

IPC: H01L23/00

Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

公开(公告)号：US09754823B2

公开(公告)日：2017-09-05

申请号：US14288840

申请日：2014-05-28

Applicant: International Business Machines Corporation ,  SUSS MicroTec Photonic Systems Inc.

Inventor： Yuri M. Brovman ,  Brian M. Erwin ,  Nicholas A. Polomoff ,  Jennifer D. Schuler ,  Matthew E. Souter ,  Christopher L. Tessler

IPC: H01L21/768

CPC classification number: H01L21/76841 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

公开(公告)号：US09728440B2

公开(公告)日：2017-08-08

申请号：US14525267

申请日：2014-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Harry D. Cox ,  Brian M. Erwin ,  Jorge A. Lubguban ,  Eric D. Perfecto ,  Jennifer D. Schuler

IPC: B32B41/00 ,  H01L21/683 ,  B32B9/04 ,  B32B17/06 ,  B32B7/12 ,  B32B7/06 ,  H01L21/66

CPC classification number: H01L21/6835 ,  B32B7/06 ,  B32B7/12 ,  B32B9/04 ,  B32B17/06 ,  B32B2457/14 ,  H01L22/12 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.

公开(公告)号：US20170179042A1

公开(公告)日：2017-06-22

申请号：US14973151

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Brian W. Quinlan

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/45099

Abstract: A module includes a core, a buildup layer having a top and a bottom, the bottom contacting the core, a solder mask layer contacting the top, the solder mask including at protective feature formed on a top surface of the solder mask, and an electronic element disposed on the top surface adjacent the protecting feature.

公开(公告)号：US20170179015A1

公开(公告)日：2017-06-22

申请号：US14973158

申请日：2015-12-17

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Brian W. Quinlan

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

公开(公告)号：US20150348910A1

公开(公告)日：2015-12-03

申请号：US14822928

申请日：2015-08-11

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Harry D. Cox ,  Brian M. Erwin ,  John J. Garant ,  Ekta Misra ,  Nicholas A. Polomoff ,  Jennifer D. Schuler

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  C25D3/38 ,  C25D5/02 ,  C25D5/022 ,  C25D5/48 ,  C25D7/123 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure including a stack of conformal layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers including a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another with the first layer being in direct contact with the dielectric layer, and a conductive feature located directly on top of the fourth layer within the opening.

Abstract translation: 一种结构，其包括在电介质层的顶部和电介质层的开口内的共形层叠层，所述叠层包括第一层，第二层，第三层和第四层， 第一层与电介质层直接接触的另一层的顶部，以及直接位于开口内第四层顶部的导电特征。

公开(公告)号：US20150348831A1

公开(公告)日：2015-12-03

申请号：US14288840

申请日：2014-05-28

Applicant: International Business Machines Corporation ,  SUSS MicroTec Photonic Systems Inc.

Inventor： Yuri M. Brovman ,  Brian M. Erwin ,  Nicholas A. Polomoff ,  Jennifer D. Schuler ,  Matthew E. Souter ,  Christopher L. Tessler

IPC: H01L21/768

CPC classification number: H01L21/76841 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03614 ,  H01L2224/03632 ,  H01L2224/0381 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/1182 ,  H01L2224/13007 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

Abstract translation: 在衬底上选择性地定位阻挡层的方法包括在衬底的表面上形成阻挡层。 阻挡层由金属元素和非金属元素组成。 阻挡层也可以由金属元素和非金属元素形成。 该方法还包括在阻挡层上形成导电膜层，并在导电膜层中形成金属部分。 该方法还包括从电介质层选择性地烧蚀阻挡层的部分，以选择性地将阻挡层定位在衬底上。