公开(公告)号：US11335730B2

公开(公告)日：2022-05-17

申请号：US16702103

申请日：2019-12-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L27/24 ,  H01L45/00

Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

公开(公告)号：US20210167128A1

公开(公告)日：2021-06-03

申请号：US16702103

申请日：2019-12-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  Cheng Chi

IPC: H01L27/24 ,  H01L45/00

Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.

公开(公告)号：US10680064B2

公开(公告)日：2020-06-09

申请号：US16233825

申请日：2018-12-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Ruilong Xie ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

公开(公告)号：US10395939B2

公开(公告)日：2019-08-27

申请号：US15890859

申请日：2018-02-07

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/30 ,  H01L27/12 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/027

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US10361116B2

公开(公告)日：2019-07-23

申请号：US15926274

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Cheng Chi ,  Lin Hu ,  Kafai Lai ,  Chi-Chun Liu ,  Jed W. Pitera

IPC: H01L21/768 ,  H01L21/02 ,  G06F17/50 ,  H01L23/528 ,  H01L23/522 ,  H01L21/027

Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.

公开(公告)号：US20180211869A1

公开(公告)日：2018-07-26

申请号：US15926274

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Cheng Chi ,  Lin Hu ,  Kafai Lai ,  Chi-Chun Liu ,  Jed W. Pitera

IPC: H01L21/768 ,  H01L21/02 ,  G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  G06F17/5072 ,  H01L21/02118 ,  H01L21/02318 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.

公开(公告)号：US09929020B2

公开(公告)日：2018-03-27

申请号：US15363596

申请日：2016-11-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/30 ,  H01L21/31 ,  H01L21/82 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US20170358666A1

公开(公告)日：2017-12-14

申请号：US15631385

申请日：2017-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49 ,  H01L29/08 ,  H01L29/161 ,  H01L29/22 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20170092507A1

公开(公告)日：2017-03-30

申请号：US15363596

申请日：2016-11-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0692

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

公开(公告)号：US11916099B2

公开(公告)日：2024-02-27

申请号：US17341489

申请日：2021-06-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/51 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L29/516

Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.