公开(公告)号：US20160027776A1

公开(公告)日：2016-01-28

申请号：US14877186

申请日：2015-10-07

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

公开(公告)号：US09099401B2

公开(公告)日：2015-08-04

申请号：US14028827

申请日：2013-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.

Abstract translation: 半导体器件包括第一组和第二组平行翅片，每组散热片具有相同数量的翅片，并且相邻散热片之间的间距低于相关光刻工艺的最小间距，其中第一组和第二组翅片之间的间隔 大于相邻翅片之间的间距; 在第一和第二组翅片上的门结构; 合并源区域，其在所述栅极结构的第一侧上连接所述第一和第二组翅片; 以及在栅极结构的第二侧连接第一组翅片和第二组翅片的合流漏极区域。

公开(公告)号：US09059019B2

公开(公告)日：2015-06-16

申请号：US13954453

申请日：2013-07-30

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

Abstract translation: 具有掺杂阱区的半导体器件包括形成在半导体器件的衬底部分上的掺杂衬底层。 掺杂衬底层沿着第一方向延伸以限定垂直于第一方向的长度和第二方向以限定宽度。 在掺杂衬底层上形成多个翅片，并且在每个鳍片之间形成氧化物衬底层。 至少一个栅极形成在氧化物衬底层上并延伸穿过多个翅片中的至少一个翅片。

公开(公告)号：US20150048430A1

公开(公告)日：2015-02-19

申请号：US14028827

申请日：2013-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/78

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure.

Abstract translation: 半导体器件包括第一组和第二组平行翅片，每组散热片具有相同数量的翅片，并且相邻散热片之间的间距低于相关光刻工艺的最小间距，其中第一和第二组翅片之间的间隔 大于相邻翅片之间的间距; 在第一和第二组翅片上的门结构; 合并源区域，其在所述栅极结构的第一侧上连接所述第一和第二组翅片; 以及在栅极结构的第二侧连接第一组翅片和第二组翅片的合流漏极区域。

公开(公告)号：US20150048429A1

公开(公告)日：2015-02-19

申请号：US13968807

申请日：2013-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/311 ,  H01L29/78

CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned.

Abstract translation: 半导体器件和侧壁图像传输方法，在硬掩模上旋转。 用于形成翅片的方法包括通过包括顶部和底部绝缘体层的层叠层和在基底上待图案化的层形成沟槽; 各向同性蚀刻顶部和底部绝缘体层; 在所述沟槽中形成硬掩模材料至所述底部绝缘体层的水平面; 各向同性蚀刻顶部绝缘体层; 并且将底部绝缘体层和待图案化的层蚀刻到衬底上以从待图案化的层形成翅片。

公开(公告)号：US08957478B2

公开(公告)日：2015-02-17

申请号：US13925105

申请日：2013-06-24

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

公开(公告)号：US20140346640A1

公开(公告)日：2014-11-27

申请号：US14457176

申请日：2014-08-12

Applicant: International Business Machines Corporation

Inventor： Chiahsun Tseng ,  David V. Horak ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/06 ,  H01L21/033

CPC classification number: H01L21/768 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/498 ,  H01L29/0692 ,  H01L45/1691 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.

公开(公告)号：US20140315380A1

公开(公告)日：2014-10-23

申请号：US13866293

申请日：2013-04-19

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L21/768 ,  H01L21/308

CPC classification number: H01L21/3083 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.

Abstract translation: 一种包括在衬底上形成四层硬掩模的方法，所述四层硬掩模包括在第一硬掩模层上方的第二硬掩模层; 在包括所述基底和所述四层硬掩模的结构的图案区域内去除所述四层硬掩模的所述第二硬掩模层的一部分; 在所述四层硬掩模之上形成一组侧壁间隔物以限定器件图案; 以及将所述器件图案的一部分转移到所述衬底中并且在所述结构的图案区域内。

公开(公告)号：US10170471B2

公开(公告)日：2019-01-01

申请号：US15292187

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/165

Abstract: A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

公开(公告)号：US10020303B2

公开(公告)日：2018-07-10

申请号：US14666464

申请日：2015-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for forming semiconductor devices having non-merged fin extensions. Methods for forming semiconductor devices include forming trenches in an insulator layer of a substrate. Fins are formed in the trenches and a dummy gate is formed over the fins, leaving a source and drain region exposed. The fins are etched below a surface level of a surrounding insulator layer. Fin extensions are epitaxially grown from the etched fins.