公开(公告)号：US20200126805A1

公开(公告)日：2020-04-23

申请号：US16165786

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Muthumanickam Sankarapandian ,  Richard A. Conti ,  Michael P. Belyansky

IPC: H01L21/311 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 Å/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.

公开(公告)号：US20190334017A1

公开(公告)日：2019-10-31

申请号：US16505411

申请日：2019-07-08

Applicant: International Business Machines Corporation

Inventor： Shogo Mochizuki ,  Michael P. Belyansky ,  Choonghyun Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234

Abstract: A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.

公开(公告)号：US20180166278A1

公开(公告)日：2018-06-14

申请号：US15825301

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Ravi K. Bonam ,  Anuja Desilva ,  Scott Halle

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  G03F7/00 ,  H01L21/02172 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02356 ,  H01L21/0332 ,  H05K999/99

Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.

公开(公告)号：US09613956B1

公开(公告)日：2017-04-04

申请号：US15183154

申请日：2016-06-15

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Kangguo Cheng ,  Ramachandra Divakaruni

IPC: H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A technique relates to punchthrough stop (PTS) doping in bulk fin field effect transistors. Fins are formed on a substrate, and each pair of the fins has a fin pitch. Each of the fins has an undoped fin channel and a punchthrough stop doping region underneath the undoped fin channel. A narrow shallow trench isolation trench is formed between the fin pitch of the fins. A wide shallow trench isolation trench is formed at an outside edge of the fins. A doped layer fills the narrow shallow trench isolation trench and the wide shallow trench isolation trench. A vertical thickness of the doped layer in the narrow shallow trench isolation trench is greater than a vertical thickness of the wide shallow trench isolation trench.

公开(公告)号：US12300615B2

公开(公告)日：2025-05-13

申请号：US18056393

申请日：2022-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta Ghate Farooq ,  Qianwen Chen ,  Shahid Butt ,  Eric Perfecto ,  Michael P. Belyansky ,  Katsuyuki Sakuma ,  John Knickerbocker

IPC: H01L23/535 ,  B32B43/00 ,  H01L21/683 ,  H01L23/522 ,  H01L23/528

Abstract: A stack structure that includes: a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and the handler wafer, wherein one or both of the device wafer and the handler wafer have a release layer that is configured to be substantially or completely vaporized by infrared ablation when exposed to an infrared laser energy. The device wafer includes at least two consecutive layers adjacent the bonding structure that together include a plurality of fill portions that substantially or completely disable entry of the infrared laser energy into a plurality of layers of the device wafer below the two consecutive layers adjacent the bonding structure.

公开(公告)号：US10832973B2

公开(公告)日：2020-11-10

申请号：US16854850

申请日：2020-04-21

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Kangguo Cheng ,  Michael P. Belyansky ,  Oleg Gluschenkov ,  Richard A. Conti ,  James Kelly ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L27/12 ,  H01L23/60 ,  H01L21/765 ,  H01L27/092 ,  H01L21/84 ,  H01L29/78

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

公开(公告)号：US20200287048A1

公开(公告)日：2020-09-10

申请号：US16841019

申请日：2020-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Ruqiang Bao ,  Michael P. Belyansky ,  Andrew M. Greene ,  Gen Tsutsui

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

公开(公告)号：US20200266111A1

公开(公告)日：2020-08-20

申请号：US16854850

申请日：2020-04-21

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Kangguo Cheng ,  Michael P. Belyansky ,  Oleg Gluschenkov ,  Richard A. Conti ,  James Kelly ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L27/12 ,  H01L23/60 ,  H01L21/765 ,  H01L21/84 ,  H01L27/092

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

公开(公告)号：US10734245B2

公开(公告)日：2020-08-04

申请号：US16165786

申请日：2018-10-19

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Muthumanickam Sankarapandian ,  Richard A. Conti ,  Michael P. Belyansky

IPC: H01L21/311 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/02

Abstract: Highly selective dry etching techniques for VFET STI recess are provided. In one aspect, a method for dry etching includes: contacting a wafer including an oxide with at least one etch gas under conditions sufficient to etch the oxide at a rate of less than about 30 Å/min; removing a byproduct of the etch from the wafer using a thermal treatment; and repeating the contacting step followed by the removing step multiple times until a desired recess of the oxide has been achieved. A method of forming a VFET device is also provided.

公开(公告)号：US20200243527A1

公开(公告)日：2020-07-30

申请号：US16847451

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.