公开(公告)号：US20180269383A1

公开(公告)日：2018-09-20

申请号：US15972423

申请日：2018-05-07

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L23/58

Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.

公开(公告)号：US20180240968A1

公开(公告)日：2018-08-23

申请号：US15436001

申请日：2017-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Joe Lee ,  Christopher J. Penny ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L43/08

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

公开(公告)号：US10045096B2

公开(公告)日：2018-08-07

申请号：US14934992

申请日：2015-11-06

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Jonathan H. Connell, II ,  Nalini K. Ratha ,  Michael Rizzolo

IPC: H04Q9/00 ,  A61B5/00

Abstract: Techniques for modifying user behavior and screening for impairment using a mobile feedback controller, such as a smartwatch, are provided. In one aspect, a method for monitoring a user includes the steps of: collecting real-time data from the user, wherein the data is collected via a mobile feedback controller worn by the user; determining whether the data collected from the user indicates impairment; determining appropriate corrective actions to be taken if the data collected from the user indicates impairment, otherwise continuing to collect data from the user in real-time; determining whether any action is needed; and undertaking the appropriate corrective actions if action is needed, otherwise continuing to collect data from the user in real-time.

公开(公告)号：US20180174899A1

公开(公告)日：2018-06-21

申请号：US15890568

申请日：2018-02-07

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Cornelius Brown Peethala ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76862 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: A semiconductor structure includes a dielectric layer having a trench formed therein and a barrier layer formed on a bottom and sidewalls of the trench, and on a top surface of the dielectric layer. The trench comprises a flared top gap opening and additional area at the bottom such that the top and bottom of the trench are wider than sidewalls of the trench. A thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is controlled using one or more cycles comprising forming an oxidized layer using a neutral beam oxidation and removing the oxidized layer using an etching process, such that the thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is substantially the same as the thickness of the barrier layer on sidewalls of the trench.

公开(公告)号：US09985199B1

公开(公告)日：2018-05-29

申请号：US15459876

申请日：2017-03-15

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L23/58 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L23/58 ,  H01L43/10 ,  H01L43/12

Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.

公开(公告)号：US09984923B2

公开(公告)日：2018-05-29

申请号：US15198516

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Cornelius Brown Peethala ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76862 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method of forming a semiconductor structure includes forming at least one trench in a dielectric layer, forming a barrier layer on a bottom of said at least one trench, sidewalls of said at least one trench and a top surface of the dielectric layer, the barrier layer having a non-uniform thickness, and selectively thinning at least a first portion of the barrier layer using one or more cycles comprising forming an oxidized layer in the first portion of the barrier layer using a neutral beam oxidation and removing the oxidized layer using an etching process.

公开(公告)号：US20180114752A1

公开(公告)日：2018-04-26

申请号：US15426679

申请日：2017-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53276 ,  H01L23/5329 ,  H01L29/78696

Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.

公开(公告)号：US09941134B2

公开(公告)日：2018-04-10

申请号：US15583638

申请日：2017-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC: H01L21/762 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US20180076034A1

公开(公告)日：2018-03-15

申请号：US15810454

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Sean D. Burns ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L21/033 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76816

Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness Ts. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than Ts, using the first trim mask layer as an etch mask.

公开(公告)号：US20180005937A1

公开(公告)日：2018-01-04

申请号：US15198962

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Benjamin David Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Michael Rizzolo ,  Nicole Adelle Saulnier

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.