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公开(公告)号：US10157789B2
公开(公告)日：2018-12-18
申请号：US15239178
申请日：2016-08-17
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/532
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
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公开(公告)号：US09799552B2
公开(公告)日：2017-10-24
申请号：US14949386
申请日：2015-11-23
IPC分类号： H01L21/76 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/528
CPC分类号： H01L21/76814 , H01L21/76802 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L21/76888 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53266
摘要： A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.
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公开(公告)号：US20170148673A1
公开(公告)日：2017-05-25
申请号：US14945640
申请日：2015-11-19
IPC分类号： H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L21/76877 , H01L21/76831 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L23/5226 , H01L23/53209 , H01L23/53223 , H01L23/53238
摘要： A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.
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公开(公告)号：US20170092538A1
公开(公告)日：2017-03-30
申请号：US14966248
申请日：2015-12-11
发明人： Terry A. Spooner , Wei Wang , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L23/53238 , H01L21/32136 , H01L21/76805 , H01L21/76814 , H01L21/76826 , H01L21/7684 , H01L21/76877 , H01L21/76883 , H01L23/53295
摘要： A method of making an interconnect structure includes forming an opening within a dielectric material layer disposed on a substrate including a conductive material, the opening extending from a first surface to a second surface of the dielectric material layer and being in contact with a portion of the substrate; performing a plasma treatment process to chemically enrich exposed surfaces of the dielectric material that line the opening to form a chemically-enriched dielectric surface layer that included an element in a higher concentration than a remaining portion of the dielectric material layer; performing a chemical treatment process to remove a metal contact product from the portion of the substrate that is in contact with the opening; and disposing a conductive material in the opening to substantially fill the opening and form the interconnect structure.
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45.发明授权公开(公告)号：US09548243B1
公开(公告)日：2017-01-17
申请号：US14755647
申请日：2015-06-30
发明人： Benjamin D. Briggs , Lawrence A. Clevenger , Michael Rizzolo , Terry A. Spooner , Theodorus E. Standaert
IPC分类号： H01L21/768 , H01L21/31 , H01L21/311 , H01L21/3105
CPC分类号： H01L21/76816 , H01L21/0332 , H01L21/0335 , H01L21/0337 , H01L21/0338 , H01L21/31053 , H01L21/31144 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L23/5329
摘要： A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.
摘要翻译： 一种形成通孔的方法，其包括在层叠介电层上存在的硬掩模层上的多个心轴上形成侧壁间隔物。 使用侧壁间隔件和多个心轴的一部分来蚀刻硬掩模层以形成硬掩模材料的第一支柱。 使用硬掩模材料的第一柱作为掩模蚀刻层间电介质层以限定第一通孔。 多个心轴被移除。 使用间隔物蚀刻硬掩模层以限定硬掩模材料的第二支柱。 使用硬掩模材料的第二柱蚀刻层间电介质层以提供第二通孔。
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公开(公告)号：US20160379929A1
公开(公告)日：2016-12-29
申请号：US15152981
申请日：2016-05-12
申请人： International Business Machines Corporation , Tokyo Electron Limited , STMicroelectronics, Inc.
发明人： Yannick Feurprier , Joe Lee , Lars W. Liebmann , Yann Mignot , Terry A. Spooner , Douglas M. Trickett , Mehmet Yilmaz
IPC分类号： H01L23/522 , H01L21/321 , H01L21/033 , H01L23/528 , H01L21/768 , H01L21/311
CPC分类号： H01L23/5226 , H01L21/0332 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76877 , H01L21/76897 , H01L23/528 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.
摘要翻译： 一种用于在集成电路中形成通孔的方法包括：图案化第一硬掩模中的第一开口，设置在第一有机自平面化聚合物（OPL）层上的第一硬掩模，去除第一OPL层的暴露部分以限定空腔 去除所述空腔中的第二硬掩模的暴露部分，去除设置在所述第二硬掩模下方的第一介电层的暴露部分以进一步限定所述空腔，去除所述空腔中的第一盖层的暴露部分，去除暴露部分 以进一步限定所述空腔，去除第二盖层的暴露部分以进一步限定所述空腔，在所述空腔中的第二导电材料上移除衬里层的暴露部分，以及在所述腔中沉积导电材料 腔。
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47.发明申请VIA FORMATION USING SIDEWALL IMAGE TRANSFER PROCESS TO DEFINE LATERAL DIMENSION 有权通过使用边框图像转移过程来形成侧向尺寸公开(公告)号：US20160336225A1
公开(公告)日：2016-11-17
申请号：US14710894
申请日：2015-05-13
发明人： Shyng-Tsong Chen , Cheng Chi , Chi-Chun Liu , Sylvie M. Mignot , Yann A. Mignot , Hosadurga K. Shobha , Terry A. Spooner , Wenhui Wang , Yongan Xu
IPC分类号： H01L21/768 , H01L23/528 , H01L23/535
CPC分类号： H01L21/76897 , H01L21/76802 , H01L21/76811 , H01L21/76816 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L23/5329
摘要： A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.
摘要翻译： 提供了形成通孔到半导体器件的下层的方法。 该方法可以包括使用侧壁图像转移过程在下层上形成柱。 介电层形成在柱和下层之上; 以及图案化在所述电介质层上的通孔掩模，所述通孔掩模具有至少部分地与所述支柱重叠的掩模开口。 使用通孔掩模在电介质层中蚀刻通孔开口，掩模开口在第一方向上限定通孔开口的第一横向尺寸，并且柱沿不同于第一方向的第二方向限定通孔开口的第二横向尺寸 方向。 通孔开口填充有导体以形成通孔。 还提供了半导体器件和通孔结构。
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公开(公告)号：US09373582B1
公开(公告)日：2016-06-21
申请号：US14749140
申请日：2015-06-24
申请人： International Business Machines Corporation , Tokyo Electron Limited , STMicroelectronics, Inc.
发明人： Yannick Feurprier , Joe Lee , Lars W. Liebmann , Yann Mignot , Terry A. Spooner , Douglas M. Trickett , Mehmet Yilmaz
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/0332 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76877 , H01L21/76897 , H01L23/528 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.
摘要翻译： 用于在集成电路中形成通孔的方法包括：图案化第一硬掩模中的第一开口，设置在第一有机自平面化聚合物（OPL）层上的第一硬掩模，去除第一OPL层的暴露部分以限定空腔 去除所述空腔中的第二硬掩模的暴露部分，去除设置在所述第二硬掩模下方的第一介电层的暴露部分以进一步限定所述空腔，去除所述空腔中的第一盖层的暴露部分，去除暴露部分 以进一步限定所述空腔，去除第二盖层的暴露部分以进一步限定所述空腔，在所述空腔中的第二导电材料上移除衬里层的暴露部分，以及在所述腔中沉积导电材料 腔。
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公开(公告)号：US11901224B2
公开(公告)日：2024-02-13
申请号：US16857408
申请日：2020-04-24
IPC分类号： H01L21/768 , H01L21/67 , H01L21/66
CPC分类号： H01L21/76864 , H01L21/67288 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L22/12
摘要： Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
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50.发明公开公开(公告)号：US20230165156A1
公开(公告)日：2023-05-25
申请号：US17534485
申请日：2021-11-24
IPC分类号： H01L43/12 , H01L43/10 , H01L43/02 , H01L43/08 , G11C11/16 , H01L27/22 , H01L21/768 , H01L23/522
CPC分类号： H01L43/12 , H01L43/10 , H01L43/02 , H01L43/08 , G11C11/161 , H01L27/222 , H01L21/76885 , H01L23/5226
摘要： Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.
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