公开(公告)号：US07015500B2

公开(公告)日：2006-03-21

申请号：US10361024

申请日：2003-02-10

Applicant: Won-bong Choi ,  In-kyeong Yoo ,  Jae-uk Chu

Inventor： Won-bong Choi ,  In-kyeong Yoo ,  Jae-uk Chu

IPC: H01B7/08 ,  H01L35/24

CPC classification number: B82Y10/00 ,  G11C13/025 ,  G11C2213/17 ,  Y10S977/943

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract translation: 一种由碳纳米管存储器件及其形成方法形成的快速，可靠，高度集成的存储器件，其中碳纳米管存储器件包括衬底，源电极，漏电极，具有高电的碳纳米管和 热导率，具有优异电荷存储能力的存储单元和栅电极。 源电极和漏电极在它们之间以预定间隔布置在衬底上并经受电压。 碳纳米管将源电极连接到漏电极并用作电荷运动的通道。 存储单元位于碳纳米管之上，并存储来自碳纳米管的电荷。 栅电极形成为与存储单元的上表面接触，并控制从碳纳米管流入存储单元的电荷量。

公开(公告)号：US06999346B2

公开(公告)日：2006-02-14

申请号：US10774456

申请日：2004-02-10

Applicant: In-kyeong Yoo ,  Byong-man Kim

Inventor： In-kyeong Yoo ,  Byong-man Kim

IPC: G11C13/07

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.

公开(公告)号：US20050145835A1

公开(公告)日：2005-07-07

申请号：US11057469

申请日：2005-02-15

Applicant: In-kyeong Yoo ,  Chang-wook Moon ,  Soo-hwan Jeong ,  Dong-wook Kim

Inventor： In-kyeong Yoo ,  Chang-wook Moon ,  Soo-hwan Jeong ,  Dong-wook Kim

IPC: G03F7/20 ,  H01J1/312 ,  H01J9/02 ,  H01J37/06 ,  H01J37/073 ,  H01J37/305 ,  H01L21/027 ,  H01L29/06 ,  H01L21/00

CPC classification number: B82Y10/00 ,  H01J1/312 ,  H01J9/022 ,  H01J9/027 ,  H01J2237/31774 ,  H01J2237/31783

Abstract: An emitter for an electron-beam projection lithography (EPL) system and a manufacturing method therefor are provided. The electron-beam emitter includes a substrate, an insulating layer overlying the substrate, and a gate electrode including a base layer formed on top of the insulating layer to a uniform thickness and an electron-beam blocking layer formed on the base layer in a predetermined pattern. The manufacturing method includes steps of: preparing a substrate; forming an insulating layer on the substrate; forming a base layer of a gate electrode by depositing a conductive metal on the insulating layer to a predetermined thickness; forming an electron-beam blocking layer of the gate electrode by depositing a metal capable of anodizing on the base layer to a predetermined thickness; and patterning the electron-beam blocking layer in a predetermined pattern by anodizing. The emitter provides a uniform electric field within the insulating layer and simplify the manufacturing method therefor.

公开(公告)号：US20050036379A1

公开(公告)日：2005-02-17

申请号：US10950582

申请日：2004-09-28

Applicant: Dong-wook Kim ,  In-kyeong Yoo ,  Jung-hyun Sok ,  June-key Lee

Inventor： Dong-wook Kim ,  In-kyeong Yoo ,  Jung-hyun Sok ,  June-key Lee

IPC: G11C11/15 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/22 ,  H01L29/788 ,  H01L29/792 ,  H01L43/08 ,  G11C11/14

CPC classification number: H01L27/228 ,  B82Y10/00

Abstract: A single transistor type magnetic random access memory device and a method of operating and manufacturing the same, wherein the single transistor type magnetic random access memory device includes a substrate, first and second doped regions spaced apart from each other, a gate dielectric layer on a portion of the semiconductor substrate between the first and second doped regions, a magnetic tunnel junction on the gate dielectric layer, word lines on the magnetic tunnel junction extending in a first direction which is the same direction as the second doped region, bit lines connected to the first doped region in a second direction perpendicular to the first direction, and an insulating layer covering the gate dielectric layer, the magnetic tunnel junction, and the word lines. The single transistor type magnetic random access memory device has a simple circuit structure, has a prolonged lifetime and is easy to manufacture.

公开(公告)号：US06838727B2

公开(公告)日：2005-01-04

申请号：US10602736

申请日：2003-06-25

Applicant: In-kyeong Yoo ,  Sun-ae Seo ,  Hyun-jo Kim

Inventor： In-kyeong Yoo ,  Sun-ae Seo ,  Hyun-jo Kim

IPC: H01L27/10 ,  G11C11/401 ,  G11C11/404 ,  G11C16/04 ,  H01L21/00 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/792 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L49/02

CPC classification number: H01L27/11206 ,  G11C16/0475 ,  H01L27/112

Abstract: A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data “0” or “1” is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.

Abstract translation: 具有一个晶体管和一个电阻元件作为存储装置的存储器件和用于驱动存储器件的方法包括形成在半导体衬底上的NPN型晶体管，形成在半导体衬底上以覆盖晶体管的层间绝缘膜， 形成暴露晶体管的源极区域的接触孔，通过导电插塞或绝缘膜将位数据“0”或“1”写入的电阻材料连接到晶体管的源极区域，并且导电 板接触抵抗材料。 存储器件通过延长其刷新周期而呈现出提高的集成度，降低的电流消耗，并且由于简单的存储单元结构而享有简化的制造工艺。

公开(公告)号：US08526288B2

公开(公告)日：2013-09-03

申请号：US13297713

申请日：2011-11-16

Applicant: Sung-chul Lee ,  Seung-hoon Han ,  In-kyeong Yoo

Inventor： Sung-chul Lee ,  Seung-hoon Han ,  In-kyeong Yoo

IPC: G11B7/00

CPC classification number: G11C13/06 ,  G02B5/008 ,  G02F2203/10

Abstract: An optical element and an information storage device including the same. The optical element may include an optical waveguide structure for transforming circularly polarized light into plasmon and transmitting the plasmon. The optical waveguide structure may emit a circularly polarized plasmonic field. The optical element may be used in an information storage device. For example, the information storage device may include a recording medium and a recording element for recording information on the recording medium, and the recording element may include the optical element. The information may be recorded on the recording medium by using the circularly polarized plasmonic field generated by the optical element.

Abstract translation: 光学元件和包括该元件的信息存储装置。 光学元件可以包括用于将圆偏振光转换成等离子体并传输等离子体的光波导结构。 光波导结构可以发射圆偏振等离子体场。 光学元件可以用在信息存储装置中。 例如，信息存储装置可以包括用于在记录介质上记录信息的记录介质和记录元件，并且记录元件可以包括光学元件。 信息可以通过使用由光学元件产生的圆偏振等离子体场来记录在记录介质上。

公开(公告)号：US08357992B2

公开(公告)日：2013-01-22

申请号：US12659516

申请日：2010-03-11

Applicant: Ho-jung Kim ,  In-kyeong Yoo ,  Chang-jung Kim ,  Ki-ha Hong

Inventor： Ho-jung Kim ,  In-kyeong Yoo ,  Chang-jung Kim ,  Ki-ha Hong

IPC: H01L23/52 ,  H01L29/00

CPC classification number: H01L27/222 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/73 ,  G11C2213/79 ,  H01L27/24

Abstract: The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines.

Abstract translation: 非易失性存储器件可以包括衬底，在垂直方向上的衬底上的多个第一信号线，具有连接到多个第一信号线的端部的多个存储器单元，垂直于第一信号线的多个第二信号线 基板上的多个第一信号线，并且各自连接到多个存储单元的另一端，以及多个选择元件，并且连接到多个第一信号线中的至少两个。

公开(公告)号：US08203863B2

公开(公告)日：2012-06-19

申请号：US12801533

申请日：2010-06-14

Applicant: Ho-jung Kim ,  In-kyeong Yoo ,  Jai-kwang Shin ,  Chang-jung Kim ,  Myoung-jae Lee ,  Ki-ha Hong

Inventor： Ho-jung Kim ,  In-kyeong Yoo ,  Jai-kwang Shin ,  Chang-jung Kim ,  Myoung-jae Lee ,  Ki-ha Hong

IPC: G11C11/00 ,  G11C8/00

CPC classification number: G11C8/08 ,  G11C5/063 ,  G11C11/21 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0069 ,  G11C15/04 ,  G11C2013/0073 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/147 ,  H01L45/148

Abstract: A nonvolatile memory cell may include a bidirectional switch having a first threshold voltage when a forward current is applied to the bidirectional switch and a second threshold voltage when a reverse current is applied to the bidirectional switch; and a variable resistor connected to the bidirectional switch in series. A state of resistance of the variable resistor may be controlled according to voltage applied to the variable resistor. A sum of a magnitude of the first threshold voltage and a magnitude of the second threshold voltage may be greater than a write voltage that is used to perform a write operation on the variable resistor.

Abstract translation: 当向双向开关施加正向电流时，非易失性存储单元可以包括具有第一阈值电压的双向开关，当向双向开关施加反向电流时，非易失性存储单元可包括第二阈值电压; 以及串联连接到双向开关的可变电阻器。 可变电阻器的电阻状态可以根据施加到可变电阻器的电压来控制。 第一阈值电压的大小和第二阈值电压的大小的和可以大于用于对可变电阻器执行写入操作的写入电压。

公开(公告)号：US08101983B2

公开(公告)日：2012-01-24

申请号：US11654626

申请日：2007-01-18

Applicant: Sun-ae Seo ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Wan-jun Park

Inventor： Sun-ae Seo ,  In-kyeong Yoo ,  Myoung-jae Lee ,  Wan-jun Park

IPC: H01L29/94

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device including one transistor and one resistant material and a method of manufacturing the nonvolatile memory device are provided. The nonvolatile memory device includes a substrate, a transistor formed on the substrate, and a data storage unit connected to a drain of the transistor. The data storage unit includes a data storage material layer having different resistance characteristics in different voltage ranges.

Abstract translation: 提供了包括一个晶体管和一个电阻材料的非易失性存储器件以及制造非易失性存储器件的方法。 非易失性存储器件包括衬底，形成在衬底上的晶体管，以及连接到晶体管的漏极的数据存储单元。 数据存储单元包括在不同电压范围内具有不同电阻特性的数据存储材料层。

公开(公告)号：US07842991B2

公开(公告)日：2010-11-30

申请号：US11798703

申请日：2007-05-16

Applicant: Sung-Il Cho ,  Choong-rae Cho ,  Eun-hong Lee ,  In-kyeong Yoo

Inventor： Sung-Il Cho ,  Choong-rae Cho ,  Eun-hong Lee ,  In-kyeong Yoo

IPC: H01L27/108

CPC classification number: H01L27/115 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

Abstract translation: 非易失性存储器件包括至少一个开关器件和至少一个电连接到该至少一个开关器件的存储节点。 所述至少一个存储节点包括下电极，一个或多个缺氧金属氧化物层，一个或多个数据存储层和上电极。 一个或多个金属氧化物层中的至少一个电连接到下电极。 所述一个或多个数据存储层中的至少一个电连接到所述一个或多个金属氧化物层中的至少一个。 上电极电连接到一个或多个数据存储层中的至少一个。 制造非易失性存储器件的方法包括制备至少一个开关器件并形成下电极，一个或多个金属氧化物层，一个或多个数据存储层和上电极。