公开(公告)号：US20250132239A1

公开(公告)日：2025-04-24

申请号：US19005161

申请日：2024-12-30

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Thomas Stanley Heaton ,  Shayan Kaviani ,  Yonggang Li ,  Mahdi Mohammadighaleni ,  Bai Nie ,  Dilan Seneviratne ,  Joshua James Stacey ,  Hiroki Tanaka ,  Elham Tavakoli ,  Ehsan Zamani

IPC: H01L23/498

Abstract: Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.

公开(公告)号：US20250126814A1

公开(公告)日：2025-04-17

申请号：US18984454

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H10D1/20 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.

公开(公告)号：US20250120102A1

公开(公告)日：2025-04-10

申请号：US18984426

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H10D1/20 ,  H01L23/15 ,  H01L23/538 ,  H01L25/18

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.

公开(公告)号：US20240194548A1

公开(公告)日：2024-06-13

申请号：US18065250

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Steve S. Cho ,  Hiroki Tanaka ,  Haobo Chen ,  Gang Duan ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/15 ,  C23C18/16 ,  C23C18/18 ,  C23C18/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/15 ,  C23C18/1639 ,  C23C18/165 ,  C23C18/1855 ,  C23C18/48 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1011 ,  H01L2924/1511 ,  H01L2924/15174 ,  H01L2924/15788

Abstract: Apparatus and methods for electroless surface finishing on glass. A planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. Planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. The planar surface enables finishing the substrate surface with an electroless NiPdAu process.

公开(公告)号：US20240186270A1

公开(公告)日：2024-06-06

申请号：US18074253

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Claudio A. Alvarez Barros ,  Beomseok Choi ,  Gang Duan ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC: H01L23/64 ,  H01F10/32 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01F10/3272 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655

Abstract: A microelectronic structure, a semiconductor package, an IC device assembly, and a method. The structure includes a core layer including an electrically non-conductive material; electrically conductive through core vias (TCVs) through the core layer; a dielectric layer on the core layer with electrically conductive structures extending therethrough and electrically coupled to the TCVs; and a magnetic inductor (MI) within at least one of the core layer or the build-up layer and including an antiferromagnetic (AF) structure. The AF structure includes a first ferromagnetic (FM) layer; an exchange coupling (EC) layer on the first FM layer and including a non-magnetic metal material; a second FM layer on the EC layer, the EC layer between the first FM layer and the second FM layer; and a pinning (P) layer including manganese and at least one of platinum or iridium, the second FM layer between the EC layer and the P layer.

公开(公告)号：US20240162158A1

公开(公告)日：2024-05-16

申请号：US18055605

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Sashi Shekhar Kandanur ,  Ravindranath Vithal Mahajan ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/538 ,  B81B1/00 ,  H01L23/31 ,  H01L23/467 ,  H01L23/498

CPC classification number: H01L23/5386 ,  B81B1/002 ,  H01L23/3121 ,  H01L23/467 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5384 ,  B81B2201/0214 ,  H01L24/16 ,  H01L2224/16227

Abstract: Embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (IC) die embedded in a dielectric material in the first portion of the interposer; and a second IC die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an opening at the interface, a conductive pad in the first portion is exposed in the opening, and the conductive pad is coupled to a circuit in at least one of the first IC die or the second IC die.

公开(公告)号：US20240113029A1

公开(公告)日：2024-04-04

申请号：US17957783

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Hiroki Tanaka ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/13 ,  H01L23/15 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/13 ,  H01L23/15 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/16 ,  H01L24/16

Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.

公开(公告)号：US20240112972A1

公开(公告)日：2024-04-04

申请号：US17958002

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Kristof Darmawikarta ,  Bai Nie ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Changhua Liu

IPC: H01L23/15 ,  G02B6/42 ,  G02B6/43

CPC classification number: H01L23/15 ,  G02B6/4204 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/43

Abstract: Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.

公开(公告)号：US11935857B2

公开(公告)日：2024-03-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/17 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/11 ,  H01L2924/01029 ,  H01L2924/0105

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11929330B2

公开(公告)日：2024-03-12

申请号：US17712944

申请日：2022-04-04

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Hiroki Tanaka ,  Robert May ,  Sameer Paital ,  Bai Nie ,  Jesse Jones ,  Chung Kwang Christopher Tan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/22 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.